FAIL-SAFE CIRCUIT

• Main Authors: MATOBA TERUO, OKIURA KOJI
• Format: Patent
• Language: English; Japanese
• Published: 10.01.2019
• Subjects: CONTROL OR REGULATING SYSTEMS IN GENERAL; CONTROLLING; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS ORELEMENTS; PHYSICS; REGULATING

To achieve a fail-safe circuit capable of withstanding against vibration and shock, and of being downsized.SOLUTION: A fail-safe circuit 1 includes: a pulse monitoring circuit 4 which includes a semiconductor integrated circuit and which monitors an input of a pulse signal that is output by a programmable controller 100; a pulse normality detecting relay 5 that changes to an OFF state when an abnormality occurs in the input of the pulse signal; a contact 7 for the pulse normality detecting relay which becomes an OFF state when the pulse normality detecting relay 5 is in the OFF state; a normality detecting relay 6 that becomes an OFF state when the contact 7 is in the OFF state; and a contact 9 for the normality detecting relay which is connected in series to an external load 8 connected to the programmable controller 100, becomes an OFF state when the normality detecting relay 6 is in the OFF state, and cuts off a power supply from an external power source to the external load 8.SELECTED DRAWING: Figure 1 【課題】振動・衝撃に強く、小型化が可能な、フェールセーフ回路を得る。【解決手段】フェールセーフ回路１は、半導体集積回路から構成され、プログラマブルコントローラ１００が出力するパルス信号の入力を監視するパルス監視回路４と、パルス信号の入力に異常が発生した場合にオフ状態に切り替わるパルス正常検出リレー５と、パルス正常検出リレー５がオフ状態の場合にオフ状態となるパルス正常検出リレーの接点７と、接点７がオフ状態の場合にオフ状態となる正常検出リレー６と、プログラマブルコントローラ１００に接続されている外部負荷８に直列に接続され、正常検出リレー６がオフ状態のときにオフ状態となって外部負荷８への外部電源からの電源供給を遮断する正常検出リレーの接点９とを備えている。【選択図】図１