WIRING BOARD

• Main Author: ENOKI KENJIRO
• Format: Patent
• Language: English; Japanese
• Published: 15.11.2018
• Subjects: BASIC ELECTRIC ELEMENTS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS; PRINTED CIRCUITS; SEMICONDUCTOR DEVICES

PROBLEM TO BE SOLVED: To provide a wiring board which suppresses trouble caused by deposition of an ion-based impurity as further as possible and has sufficient environmental resistance property, heat radiation property and fast responsiveness.SOLUTION: The present invention relates to a wiring board 1a comprising: a resin insulation part 2 configured by laminating multiple resin layers j1-j4, and including a front face 3 and a rear face 4 that are opposite to each other; and front-side and rear-side ceramic layers c1 and c2 which are adhered on the front face 3 and the rear face 4 of the resin insulation part 2. Between layers of the multiple resin layers j1-j4 in the resin insulation part 2, internal layer wiring 8 of a predetermined pattern is formed. Between the front and rear faces 3 and 4 of the resin insulation part 2 and the internal layer wiring 8, first and second via conductors 5 and 6 are formed while penetrating the top or bottom resin layer j1 or j4. On the front face 3 and the rear face 4 of the resin insulation part 2 where one end face of the first/second via conductor 5/6 is exposed, through-holes 11 and 12 are formed while penetrating front-side ceramic layers c1 and c4 and defining one end face of the first/second via conductor 5/6 as a bottom face.SELECTED DRAWING: Figure 1 【課題】イオン系不純物の付着による不具合を可及的に抑制し、且つ十分な耐環境特性、放熱性、および高速応答性を併有する配線基板を提供する。【解決手段】複数の樹脂層ｊ１〜ｊ４を積層してなり、対向する表面３および裏面４を有する樹脂絶縁部２と、該樹脂絶縁部２の表面３および裏面４に接着された表面側および裏面側のセラミック層ｃ１，ｃ２とを備え、樹脂絶縁部２における複数の樹脂層ｊ１〜ｊ４の層間には、所定パターンの内層配線８が形成され、樹脂絶縁部２の表面３および裏面４と内層配線８との間には、最上層または最下層の樹脂層ｊ１，ｊ４を貫通する第１・第２ビア導体５．６が形成されていると共に、第１・第２ビア導体５，６の一端面が露出する樹脂絶縁部２の表面３および裏面４には、表面側のセラミック層ｃ１，ｃ４を貫通し且つ第１・第２ビア導体５，６の一端面を底面とする貫通孔１１，１２が形成されている、配線基板１ａ。【選択図】 図１