FREQUENCY MULTIPLIER AND MEASURING APPARATUS INCLUDING THE SAME

PROBLEM TO BE SOLVED: To provide a frequency multiplier capable of suppressing output of unnecessary wave components and a measuring apparatus including the same.SOLUTION: A frequency multiplier 32 doubles an input frequency of an input signal and outputs it. The frequency multiplier includes: diode...

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Bibliographic Details
Main Authors NODA HANAKO, OKAMOTO AKIFUMI, SEKINE YUJI, ARAI SHIGEO
Format Patent
LanguageEnglish
Japanese
Published 23.08.2018
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Summary:PROBLEM TO BE SOLVED: To provide a frequency multiplier capable of suppressing output of unnecessary wave components and a measuring apparatus including the same.SOLUTION: A frequency multiplier 32 doubles an input frequency of an input signal and outputs it. The frequency multiplier includes: diodes 121 to 124 for full-wave rectifying an input signal; and a bias voltage applying section 33 for clipping a voltage of a full-wave rectified waveform obtained by the diodes 121 to 124 with a predetermined clip voltage. The bias voltage applying section 33 has a configuration to clip the voltage of the full-wave rectified waveform on the basis of a level of a frequency component different from the frequency component which is twice the input frequency.SELECTED DRAWING: Figure 2 【課題】不要波成分の出力を抑制することができる周波数逓倍器及びそれを備えた測定装置を提供する。【解決手段】周波数逓倍器32は、入力信号の入力周波数を2倍にして出力するものであって、入力信号を全波整流するダイオード121乃至124と、ダイオード121乃至124によって得られた全波整流波形の電圧を予め定められたクリップ電圧でクリップするバイアス電圧印加部33と、を備え、バイアス電圧印加部33は、入力周波数の2倍の周波数成分とは異なる周波数成分のレベルに基づいて全波整流波形の電圧をクリップする構成を有する。【選択図】図2
Bibliography:Application Number: JP20170025812