SEMICONDUCTOR DEVICE
PROBLEM TO BE SOLVED: To provide a structure of a semiconductor device with the reduced number of selection gates per one columnar semiconductor layer.SOLUTION: A semiconductor device comprises: a first columnar semiconductor layer; a first selection gate insulating film surrounding the first column...
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Main Authors | , |
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Format | Patent |
Language | English Japanese |
Published |
12.07.2018
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Subjects | |
Online Access | Get full text |
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Summary: | PROBLEM TO BE SOLVED: To provide a structure of a semiconductor device with the reduced number of selection gates per one columnar semiconductor layer.SOLUTION: A semiconductor device comprises: a first columnar semiconductor layer; a first selection gate insulating film surrounding the first columnar semiconductor layer; a first selection gate surrounding the first selection gate insulating film; a first gate insulating film surrounding an upper part of the first columnar semiconductor layer; a first contact electrode surrounding the first gate insulating film; a first bit line connected to the upper part of the first columnar semiconductor layer and an upper part of the first contact electrode; a second columnar semiconductor layer; a layer having a first charge storage layer surrounding the second columnar semiconductor layer; a first control gate surrounding the layer; a layer having a second charge storage layer surrounding the second columnar semiconductor layer; a second control gate surrounding the layer; a second gate insulating film surrounding an upper part of the second columnar semiconductor layer; a second contact electrode surrounding the second gate insulating film; and first lower internal wiring connecting a lower part of the first columnar semiconductor layer to a lower part of the second columnar semiconductor layer.SELECTED DRAWING: Figure 1
【課題】柱状半導体層一本あたりの選択ゲート数を減少させた半導体装置の構造を提供する。【解決手段】本発明の半導体装置は、第1の柱状半導体層と、これを取り囲む第1の選択ゲート絶縁膜と、これを取り囲む第1の選択ゲートと、第1の柱状半導体層上部を取り囲む第1のゲート絶縁膜と、第1のゲート絶縁膜を取り囲む第1のコンタクト電極と、第1の柱状半導体層上部と第1のコンタクト電極上部に接続された第1のビット線と、第2の柱状半導体層と、これを取り囲む第1の電荷蓄積層を有する層と、これを取り囲む第1の制御ゲートと、第2の柱状半導体層を取り囲む第2の電荷蓄積層を有する層と、これを取り囲む第2の制御ゲートと、第2の柱状半導体層上部を取り囲む第2のゲート絶縁膜と、第2のゲート絶縁膜を取り囲む第2のコンタクト電極と、第1の柱状半導体層の下部と第2の柱状半導体層の下部を接続する第1の下部内部配線、を有する。【選択図】図1 |
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Bibliography: | Application Number: JP20180027000 |