SiC EPITAXIAL WAFER AND SEMICONDUCTOR DEVICE
PROBLEM TO BE SOLVED: To provide a SiC epitaxial wafer capable of reducing the resistance of an impurity layer.SOLUTION: A SiC epitaxial wafer comprises: a 4H-SiC substrate 100; a first p type SiC epitaxial layer 102 including a p type impurity (an element A) and a n type impurity (an element D) in...
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26.04.2018
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Abstract | PROBLEM TO BE SOLVED: To provide a SiC epitaxial wafer capable of reducing the resistance of an impurity layer.SOLUTION: A SiC epitaxial wafer comprises: a 4H-SiC substrate 100; a first p type SiC epitaxial layer 102 including a p type impurity (an element A) and a n type impurity (an element D) in which a combination of the element A and the element D is Al, Ga or In and at least one of N, B and P and a concentration ratio of the element D to the element A is 0.33-1.0; a second n type SiC epitaxial layer 106 provided between the SiC substrate and the first SiC epitaxial layer; and a third p type SiC epitaxial layer 108 provided between the second and first SiC epitaxial layers and having a p type impurity concentration lower than that of the first SiC epitaxial layer. The SiC substrate is a n type and has a n type impurity concentration higher than that of the second SiC epitaxial layer, and the concentration of the element A is 1×10- 1×10cm.SELECTED DRAWING: Figure 10
【課題】不純物層の抵抗を低減したSiCエピタキシャルウェハの提供。【解決手段】4H−SiC基板100と、p型不純物(元素A)とn型不純物(元素D)を含有し、元素Aと元素Dが、Al、Ga又はInとN、BとPの少なくとも一方の組み合わせで、元素Dの元素Aに対する濃度比が0.33〜1.0、p型の第1のSiCエピタキシャル層102と、SiC基板と第1のSiCエピタキシャル層の間に設けられるn型の第2のSiCエピタキシャル層106と、第2のSiCエピタキシャル層と第1のSiCエピタキシャル層の間に設けられ、p型不純物濃度が、第1のSiCエピタキシャル層より低いp型の第3のSiCエピタキシャル層108と、を備え、SiC基板がn型で、n型不純物濃度が、第2のSiCエピタキシャル層より高く、元素Aの濃度が1×1018〜1×1022cm−3であるSiCエピタキシャルウェハ。【選択図】図10 |
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AbstractList | PROBLEM TO BE SOLVED: To provide a SiC epitaxial wafer capable of reducing the resistance of an impurity layer.SOLUTION: A SiC epitaxial wafer comprises: a 4H-SiC substrate 100; a first p type SiC epitaxial layer 102 including a p type impurity (an element A) and a n type impurity (an element D) in which a combination of the element A and the element D is Al, Ga or In and at least one of N, B and P and a concentration ratio of the element D to the element A is 0.33-1.0; a second n type SiC epitaxial layer 106 provided between the SiC substrate and the first SiC epitaxial layer; and a third p type SiC epitaxial layer 108 provided between the second and first SiC epitaxial layers and having a p type impurity concentration lower than that of the first SiC epitaxial layer. The SiC substrate is a n type and has a n type impurity concentration higher than that of the second SiC epitaxial layer, and the concentration of the element A is 1×10- 1×10cm.SELECTED DRAWING: Figure 10
【課題】不純物層の抵抗を低減したSiCエピタキシャルウェハの提供。【解決手段】4H−SiC基板100と、p型不純物(元素A)とn型不純物(元素D)を含有し、元素Aと元素Dが、Al、Ga又はInとN、BとPの少なくとも一方の組み合わせで、元素Dの元素Aに対する濃度比が0.33〜1.0、p型の第1のSiCエピタキシャル層102と、SiC基板と第1のSiCエピタキシャル層の間に設けられるn型の第2のSiCエピタキシャル層106と、第2のSiCエピタキシャル層と第1のSiCエピタキシャル層の間に設けられ、p型不純物濃度が、第1のSiCエピタキシャル層より低いp型の第3のSiCエピタキシャル層108と、を備え、SiC基板がn型で、n型不純物濃度が、第2のSiCエピタキシャル層より高く、元素Aの濃度が1×1018〜1×1022cm−3であるSiCエピタキシャルウェハ。【選択図】図10 |
Author | NISHIO JOJI SHIMIZU TATSUO SHINOHE TAKASHI OTA CHIHARU |
Author_xml | – fullname: NISHIO JOJI – fullname: SHIMIZU TATSUO – fullname: OTA CHIHARU – fullname: SHINOHE TAKASHI |
BookMark | eNrjYmDJy89L5WTQCc50VnAN8AxxjPB09FEId3RzDVJw9HNRCHb19XT293MJdQ7xD1JwcQ3zdHblYWBNS8wpTuWF0twMSm6uIc4euqkF-fGpxQWJyal5qSXxXgFGBoYWBmam5sbmjsZEKQIA1oAnag |
ContentType | Patent |
DBID | EVB |
DatabaseName | esp@cenet |
DatabaseTitleList | |
Database_xml | – sequence: 1 dbid: EVB name: esp@cenet url: http://worldwide.espacenet.com/singleLineSearch?locale=en_EP sourceTypes: Open Access Repository |
DeliveryMethod | fulltext_linktorsrc |
Discipline | Medicine Chemistry Sciences |
DocumentTitleAlternate | SiCエピタキシャルウェハおよび半導体装置 |
ExternalDocumentID | JP2018065737A |
GroupedDBID | EVB |
ID | FETCH-epo_espacenet_JP2018065737A3 |
IEDL.DBID | EVB |
IngestDate | Fri Jul 19 13:03:16 EDT 2024 |
IsOpenAccess | true |
IsPeerReviewed | false |
IsScholarly | false |
Language | English Japanese |
LinkModel | DirectLink |
MergedId | FETCHMERGED-epo_espacenet_JP2018065737A3 |
Notes | Application Number: JP20170178373 |
OpenAccessLink | https://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20180426&DB=EPODOC&CC=JP&NR=2018065737A |
ParticipantIDs | epo_espacenet_JP2018065737A |
PublicationCentury | 2000 |
PublicationDate | 20180426 |
PublicationDateYYYYMMDD | 2018-04-26 |
PublicationDate_xml | – month: 04 year: 2018 text: 20180426 day: 26 |
PublicationDecade | 2010 |
PublicationYear | 2018 |
RelatedCompanies | TOSHIBA CORP |
RelatedCompanies_xml | – name: TOSHIBA CORP |
Score | 3.2622807 |
Snippet | PROBLEM TO BE SOLVED: To provide a SiC epitaxial wafer capable of reducing the resistance of an impurity layer.SOLUTION: A SiC epitaxial wafer comprises: a... |
SourceID | epo |
SourceType | Open Access Repository |
SubjectTerms | AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUSPOLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE APPARATUS THEREFOR BASIC ELECTRIC ELEMENTS CHEMICAL SURFACE TREATMENT CHEMISTRY COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATIONOR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY IONIMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL COATING MATERIAL WITH METALLIC MATERIAL COATING METALLIC MATERIAL CRYSTAL GROWTH DIFFUSION TREATMENT OF METALLIC MATERIAL ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION INGENERAL METALLURGY PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITHDEFINED STRUCTURE REFINING BY ZONE-MELTING OF MATERIAL SEMICONDUCTOR DEVICES SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITHDEFINED STRUCTURE SINGLE-CRYSTAL-GROWTH SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THESURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL ORUNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL |
Title | SiC EPITAXIAL WAFER AND SEMICONDUCTOR DEVICE |
URI | https://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20180426&DB=EPODOC&locale=&CC=JP&NR=2018065737A |
hasFullText | 1 |
inHoldings | 1 |
isFullTextHit | |
isPrint | |
link | http://utb.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwfV3dS8MwED_mFPVNpzKdShHpk8WtH2n7MKRLUrbi2tJ1s2-jTTuYgg5X8d83qZ3uaW9JDi7JweXyy-XuAO6ZrWeiAKyipQUHKCZCSppahrJAPVbYOmI5EgHOYx8Np7qXGEkD3jaxMFWe0O8qOSLXKMb1vazO69X_Ixap_lauH7MlH_p4cuM-kWt03LMEJJDJoE_DgARYxrjvhbIf_dKQYWqmswf7_B5tCnWgs4EIS1lt2xT3BA5Czu69PIXGa9qCI7wpvdaCw3Ht8ebNWvnWZ_AwWWKJhqPYSUbOs_TiuDSSHJ9IEyHLwCdTHAeRROhshOk53Lk0xkOFTzv_2-TcC7eWqF1Ak6P_og2SzQyGClO18iLXM11NzTzr2ovc6mkW6-bWJXR2MLraSe3AsegJ54iKrqFZfn4VN9zGltltJZsf2xV7Xw |
link.rule.ids | 230,309,783,888,25576,76876 |
linkProvider | European Patent Office |
linkToHtml | http://utb.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwfV3fT8IwEL4gGvFNUYPij8WYPbkIbOu2h8WMtgtD2BYYuDeydSNBEyUy479vO0F54q3pJdf2kq_Xr-3dAdwzS0tFAVhFTXJOUAyElCQxdWWO2iy3NMQyJAKchz7qTbR-rMcVeNvEwpR5Qr_L5IgcUYzjvSj36-X_JRYp_1auHtMF7_p4ciObyGt23DYFJZBJ16ZhQAIsY2z3Q9kf_cqQbqiGswf7_IxtCDjQaVeEpSy3fYp7DAchV_denEDlNalDDW9Kr9XhcLh-8ebNNfhWp_AwXmCJhl7kxJ4zkF4cl44kxyfSWNgy8MkER8FIInTqYXoGdy6NcE_hw87-Fjnrh1tTVM-hytl_3gDJYjpDudExszzTUq2TGFnasuaZ2VZN1srMC2juUHS5U3oLtV40HMwGnv_chCMhEQ8lHXQF1eLzK7_m_rZIb0o7_QDPGX5S |
openUrl | ctx_ver=Z39.88-2004&ctx_enc=info%3Aofi%2Fenc%3AUTF-8&rfr_id=info%3Asid%2Fsummon.serialssolutions.com&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Apatent&rft.title=SiC+EPITAXIAL+WAFER+AND+SEMICONDUCTOR+DEVICE&rft.inventor=NISHIO+JOJI&rft.inventor=SHIMIZU+TATSUO&rft.inventor=OTA+CHIHARU&rft.inventor=SHINOHE+TAKASHI&rft.date=2018-04-26&rft.externalDBID=A&rft.externalDocID=JP2018065737A |