SiC EPITAXIAL WAFER AND SEMICONDUCTOR DEVICE
PROBLEM TO BE SOLVED: To provide a SiC epitaxial wafer capable of reducing the resistance of an impurity layer.SOLUTION: A SiC epitaxial wafer comprises: a 4H-SiC substrate 100; a first p type SiC epitaxial layer 102 including a p type impurity (an element A) and a n type impurity (an element D) in...
Saved in:
Main Authors | , , , |
---|---|
Format | Patent |
Language | English Japanese |
Published |
26.04.2018
|
Subjects | |
Online Access | Get full text |
Cover
Loading…
Summary: | PROBLEM TO BE SOLVED: To provide a SiC epitaxial wafer capable of reducing the resistance of an impurity layer.SOLUTION: A SiC epitaxial wafer comprises: a 4H-SiC substrate 100; a first p type SiC epitaxial layer 102 including a p type impurity (an element A) and a n type impurity (an element D) in which a combination of the element A and the element D is Al, Ga or In and at least one of N, B and P and a concentration ratio of the element D to the element A is 0.33-1.0; a second n type SiC epitaxial layer 106 provided between the SiC substrate and the first SiC epitaxial layer; and a third p type SiC epitaxial layer 108 provided between the second and first SiC epitaxial layers and having a p type impurity concentration lower than that of the first SiC epitaxial layer. The SiC substrate is a n type and has a n type impurity concentration higher than that of the second SiC epitaxial layer, and the concentration of the element A is 1×10- 1×10cm.SELECTED DRAWING: Figure 10
【課題】不純物層の抵抗を低減したSiCエピタキシャルウェハの提供。【解決手段】4H−SiC基板100と、p型不純物(元素A)とn型不純物(元素D)を含有し、元素Aと元素Dが、Al、Ga又はInとN、BとPの少なくとも一方の組み合わせで、元素Dの元素Aに対する濃度比が0.33〜1.0、p型の第1のSiCエピタキシャル層102と、SiC基板と第1のSiCエピタキシャル層の間に設けられるn型の第2のSiCエピタキシャル層106と、第2のSiCエピタキシャル層と第1のSiCエピタキシャル層の間に設けられ、p型不純物濃度が、第1のSiCエピタキシャル層より低いp型の第3のSiCエピタキシャル層108と、を備え、SiC基板がn型で、n型不純物濃度が、第2のSiCエピタキシャル層より高く、元素Aの濃度が1×1018〜1×1022cm−3であるSiCエピタキシャルウェハ。【選択図】図10 |
---|---|
Bibliography: | Application Number: JP20170178373 |