PATTERN TREATMENT METHOD

PROBLEM TO BE SOLVED: To provide a high resolution pattern treatment method using a solvent development type negative chemically amplified resist in the manufacture of a semiconductor device.SOLUTION: A pattern treatment method is provided, which comprises: (a) providing a semiconductor substrate co...

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Bibliographic Details
Main Authors PARK JONG KEUN, PHILLIP D HUSTAD, LI MINGQI, SUNG JIN WUK, JOSHUA A KAITZ, VIPUL JAIN, WU CHUNYI
Format Patent
LanguageEnglish
Japanese
Published 01.02.2018
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Summary:PROBLEM TO BE SOLVED: To provide a high resolution pattern treatment method using a solvent development type negative chemically amplified resist in the manufacture of a semiconductor device.SOLUTION: A pattern treatment method is provided, which comprises: (a) providing a semiconductor substrate comprising a patterned feature on a surface thereof; (b) applying a pattern treatment composition on (a), the pattern treatment composition comprising an organic solvent and a block copolymer comprising (i) a first block including a first unit formed from 4-vinyl-pyridine and (ii) a second block including a first unit formed from a vinyl aromatic monomer; and (c) removing the pattern treatment composition from the substrate. A pattern spacing can be reduced compared to a pattern spacing of the patterned feature prior to the application of the pattern treatment composition.SELECTED DRAWING: None 【課題】半導体デバイス製造に於いて、溶剤現像ネガ型化学増幅レジストを使用した高解像度パターン処理法を提供する。【解決手段】(a)表面上にパターン形成特徴部を備える半導体基板を準備し、(b)(a)上に、(i)4−ビニル−ピリジンから形成される第1の単位を含む第1のブロックと、(ii)ビニル芳香族モノマーから形成される第1の単位を含む第2のブロック、とを含むブロックコポリマー、及び有機溶媒を含む、パターン処理組成物を塗布し、(c)パターン処理組成物を基板から除去する、パターン処理法。パターン処理組成物を塗布する前のパターン形成特徴部のパターン間隔と比較して、パターン間隔を低減できる。【選択図】なし
Bibliography:Application Number: JP20170142496