GATE DRIVE CIRCUIT

PROBLEM TO BE SOLVED: To provide a gate drive circuit suppressing a turn-off loss of a switching element while achieving protection of the switching element.SOLUTION: Each of gate drive circuits 1A-1C according to one embodiment comprises: a gate output terminal connected with a gate of a switching...

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Main Authors UEDA KAZUHIRO, KUZUMAKI ATSUHIKO, TAKIMOTO KAZUYASU, TAI HIROMICHI, MORIKAWA RYUICHI, OBE TOSHIHARU, HIRANO MAKIKO, ITO HIROAKI
Format Patent
LanguageEnglish
Japanese
Published 14.12.2017
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Summary:PROBLEM TO BE SOLVED: To provide a gate drive circuit suppressing a turn-off loss of a switching element while achieving protection of the switching element.SOLUTION: Each of gate drive circuits 1A-1C according to one embodiment comprises: a gate output terminal connected with a gate of a switching element 3; a pulse generation device 5 that outputs a pulse for controlling gate potential of the switching element 3; a first resistor 6 connected between the pulse generation device 5 and the gate output terminal; a second resistor 7 connected in parallel to the first resistor 6 between the pulse generation device 5 and the gate output terminal; a changeover switch 14 that connects one of the first resistor 6 and the second resistor 7 to the pulse generation device 5; a comparator 12 that compares a signal supplied to an input terminal with a reference voltage Vref and outputs a signal for switching the changeover switch 14; and an inductance 8 whose one end is connected to an emitter of the switching element 3, and whose other end is connected to the input terminal of the comparator 12 via a diode 9 and voltage dividing resistors 10 and 11.SELECTED DRAWING: Figure 1 【課題】 スイッチング素子の保護を図るとともに、スイッチング素子のターンオフ損失を抑制するゲート駆動回路を提供する。【解決手段】 実施形態によるゲート駆動回路1A〜1Cは、スイッチング素子3のゲートと接続したゲート出力端子と、スイッチング素子3のゲート電位を制御するパルスを出力するパルス発生装置5と、パルス発生装置5とゲート出力端子との間に接続した第1抵抗器6と、パルス発生装置5とゲート出力端子との間において、第1抵抗器6と並列に接続した第2抵抗器7と、第1抵抗器6と第2抵抗器7との一方をパルス発生装置5と接続する切替スイッチ14と、入力端子に供給された信号と参照電圧Vrefとを比較して切替スイッチ14を切替える信号を出力するコンパレータ12と、一端がスイッチング素子3のエミッタと接続し、他端がダイオード9と分圧抵抗器10、11とを介してコンパレータ12の入力端子と接続したインダクタンス8と、を備える。【選択図】図1
Bibliography:Application Number: JP20160115417