LEVEL SHIFTER

• Main Authors: SATO MANABU, BUSHNAQ SANAD SALEH KHAIREDDEEN
• Format: Patent
• Language: English; Japanese
• Published: 30.11.2017
• Subjects: BASIC ELECTRIC ELEMENTS; BASIC ELECTRONIC CIRCUITRY; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; INFORMATION STORAGE; PHYSICS; PULSE TECHNIQUE; SEMICONDUCTOR DEVICES; STATIC STORES

PROBLEM TO BE SOLVED: To achieve high reliability.SOLUTION: The level shifter includes: a first circuit which inverts a first signal SE and generates a delayed second signal DEn; a NAND circuit 65 into which the first signal SE and the second signal DEn are input; a first transistor 70 to one end of which a first voltage VLS is applied, the other end of which is connected with a power terminal Tsup and into a gate of which a third signal SEn is input; second and third transistors 66 and 67 to one ends of which a second voltage VBST is applied in common, the other ends of which are connected with a first wiring NVTD in common and a gate of which is connected with an output terminal OUT or into a gate of which a first signal SE is input; and a fourth transistor 69 one end of which is connected with a first wiring NVTD, the other of which is connected with an output terminal OUT and into a gate of which an output signal GATEP is input.SELECTED DRAWING: Figure 5 【課題】信頼性を向上する。【解決手段】実施形態に係るレベルシフタは、第１信号ＳＥを反転し且つ遅延させた第２信号ＤＥｎを生成する第１回路と、第１信号ＳＥ及び第２信号ＤＥｎが入力されるＮＡＮＤ回路６５と、一端に第１電圧ＶＬＳが印加され、他端が電源端子Ｔｓｕｐに接続され、ゲートに第３信号ＳＥｎが入力される第１トランジスタ７０と、一端に第２電圧ＶＢＳＴが共通に印加され、他端が第１配線ＮＶＴＤに共通に接続され、ゲートが出力端子ＯＵＴに接続され、あるいはゲートに第１信号ＳＥが入力される第２及び第３トランジスタ６６及び６７と、一端が第１配線ＮＶＴＤに接続され、他端が出力端子ＯＵＴに接続され、ゲートに出力信号ＧＡＴＥＰが入力される第４トランジスタ６９と、を含む。【選択図】図５