SEMICONDUCTOR STORAGE DEVICE AND MANUFACTURING METHOD OF THE SAME

• Main Authors: KUBOTA YOSHITAKA, BABA YASUYUKI, NOGUCHI MITSUHIRO
• Format: Patent
• Language: English; Japanese
• Published: 26.10.2017
• Subjects: BASIC ELECTRIC ELEMENTS; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; SEMICONDUCTOR DEVICES

PROBLEM TO BE SOLVED: To reduce an area of a hook-up region.SOLUTION: A semiconductor storage device comprises a first memory block 100_2, a first hook-up region 200_1 juxtaposed with the first memory block in a first direction and a first isolation region 300 provided between the first memory block and the first hook-up region. The first memory bock includes a plurality of first conductive layers 21 stacked on a substrate SB and first memory pillars MP provided in each of the plurality of first conductive layers; and the first hook-up region includes a plurality of second conductive layers 21 provided in the same layers with the plurality of first conductive layers; and the first isolation region includes a plurality of first insulation layers 28 which are provided in the same layers with the plurality of first conductive layers to isolate the plurality of first conductive layers and the plurality of second conductive layers.SELECTED DRAWING: Figure 8 【課題】フックアップ領域の面積削減を図る。【解決手段】半導体記憶装置は、第１メモリブロック１００＿２と、前記第１メモリブロックに対して第１方向に並ぶ第１フックアップ領域２００＿１と、前記第１メモリブロックと前記第１フックアップ領域との間に設けられた第１分離領域３００と、を具備する。前記第１メモリブロックは、基板ＳＢ上に積層された複数の第１導電層２１と、前記複数の第１導電層内に設けられた第１メモリピラーＭＰとを含み、前記第１フックアップ領域は、前記複数の第１導電層と同一層に設けられた複数の第２導電層２１を含み、前記第１分離領域は、前記複数の第１導電層と同一層に設けられ、かつ前記複数の第１導電層と前記複数の第２導電層とを分離する複数の第１絶縁層２８を含む。【選択図】 図８