DEMAPPING PROCESSING CIRCUIT, CHIP, RECEIVING DEVICE, AND LLR CALCULATION METHOD

• Main Authors: MIYASAKA HIROAKI, SHIBUYA KAZUHIKO, SATO AKIHIKO, ASAKURA SHINGO, TAKEUCHI TOMOAKI, HONDA MADOKA, NARISEI ZENICHI, SHITOMI TAKUYA, SAITO SUSUMU, MURAYAMA KENICHI, TSUCHIDA KENICHI, OKANO MASAHIRO
• Format: Patent
• Language: English; Japanese
• Published: 12.10.2017
• Subjects: BASIC ELECTRONIC CIRCUITRY; CODE CONVERSION IN GENERAL; CODING; DECODING; ELECTRIC COMMUNICATION TECHNIQUE; ELECTRICITY; TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION

PROBLEM TO BE SOLVED: To provide a logarithmic likelihood ratio (LLR) calculation method and a demapping processing circuit that keep calculation errors down and substantially reduce the amount of calculation at a time of calculation of the logarithmic likelihood ratio (LLR) in a demapping process.SOLUTION: A demapping processing circuit calculates a logarithmic likelihood ratio (LLR) using coordinates of partial ideal signal points having a large impact on results of the LLR among ideal signal points on an IQ plane by the bit when finding the LLR of each bit of reception data corresponding to a reception symbol from coordinates of the reception symbol on the IQ plane.SELECTED DRAWING: Figure 2 【課題】デマッピング処理における対数尤度比（ＬＬＲ）の計算に際して、計算誤差を抑えるとともに、計算量を大幅に削減するＬＬＲ算出方法及びデマッピング処理回路を提供する。【解決手段】ＩＱ平面における受信シンボルの座標から前記受信シンボルに対応する受信データの各ビットのＬＬＲを求める際に、ビットごとに、ＩＱ平面上の理想信号点のうち、ＬＬＲの結果に影響の大きい一部の理想信号点の座標を利用して、ＬＬＲを計算することを特徴とする。【選択図】図２