METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR DEVICE

• Main Authors: NAKAMURA HIROKI, MASUOKA FUJIO
• Format: Patent
• Language: English; Japanese
• Published: 05.10.2017
• Subjects: BASIC ELECTRIC ELEMENTS; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; SEMICONDUCTOR DEVICES

PROBLEM TO BE SOLVED: To provide a method for manufacturing a Surrounding Gate Transistor (SGT) and a structure obtained thereby.SOLUTION: A method for manufacturing a semiconductor device comprises a first step and a second step performed after the first step. The first step comprises the steps of: forming a fin-shaped semiconductor layer on a semiconductor substrate; and forming a first insulating film around the fin-shaped semiconductor layer. The second step comprises the steps of: forming a second insulating film around the fin-shaped semiconductor layer; depositing and flattening a first polysilicon on the second insulating film; forming a second resist for forming a first gate wiring and a first columnar semiconductor layer and forming a third resist for forming a first contact wiring and a second columnar semiconductor layer in the perpendicular direction with regard to the direction of the fin-shaped semiconductor layer; and forming a first dummy gate made of the first columnar semiconductor layer and the first polysilicon and a second dummy gate made of the second columnar semiconductor layer and the first polysilicon by etching the first polysilicon, the second insulating film, and the fin-shaped semiconductor layer.SELECTED DRAWING: Figure 1 【課題】ＳＧＴの製造方法とその結果得られる構造を提供する。【解決手段】半導体基板上にフィン状半導体層を形成し、前記フィン状半導体層の周囲に第１の絶縁膜を形成する第１工程と、前記第１工程の後、前記フィン状半導体層の周囲に第２の絶縁膜を形成し、前記第２の絶縁膜の上に第１のポリシリコンを堆積し平坦化し、第１のゲート配線と第１の柱状半導体層を形成するための第２のレジストと、第１のコンタクト配線と第２の柱状半導体層を形成するための第３のレジストを、前記フィン状半導体層の方向に対して垂直の方向に形成し、前記第１のポリシリコンと前記第２の絶縁膜と前記フィン状半導体層をエッチングすることにより、第１の柱状半導体層と前記第１のポリシリコンによる第１のダミーゲートと第２の柱状半導体層と前記第１のポリシリコンによる第２のダミーゲートを形成する第２工程とを有する。【選択図】図１