MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE

• Main Author: MORI KAORU
• Format: Patent
• Language: English; Japanese
• Published: 05.10.2017
• Subjects: BASIC ELECTRIC ELEMENTS; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; SEMICONDUCTOR DEVICES

PROBLEM TO BE SOLVED: To improve an electric characteristic of a semiconductor device having a DRAM cell.SOLUTION: A manufacturing method of a semiconductor device, includes: a step of designating a first design dimension of a gate electrode G1 of a selection MISFET, a second design dimension of a side wall insulation film SW1, and an initial setting condition of an ion implantation of a semiconductor region SD1; a step S2 of forming the gate electrode G1; a step S3 of measuring a first processing dimension of the gate electrode G1; a semiconductor region NM1 implantation step S7 of forming the semiconductor region NM1 to both sides of the gate electrode G1; a step S8 of forming the side wall insulation film SW1 onto the side wall of the gate electrode G1; a step S9 of measuring a second processing dimension of the side wall insulation film SW1; and a semiconductor region SD1 implantation step S10 of forming the semiconductor region SD1. In the semiconductor region SD1 implantation step, an execution condition for the initial setting condition of the ion implantation is reset on the basis of a deviation to the first and second design dimensions of the first and second processing dimensions, and the semiconductor region SD1 implantation steps are executed.SELECTED DRAWING: Figure 3 【課題】ＤＲＡＭセルを有する半導体装置の電気特性を向上する。【解決手段】半導体装置の製造方法は、選択ＭＩＳＦＥＴのゲート電極Ｇ１の第１設計寸法、側壁絶縁膜ＳＷ１の第２設計寸法、半導体領域ＳＤ１のイオン注入の初期設定条件を求めておく工程、ゲート電極Ｇ１を形成する工程Ｓ２、ゲート電極Ｇ１の第１加工寸法を測定する工程Ｓ３、ゲート電極Ｇ１の両端に半導体領域ＮＭ１を形成する半導体領域ＮＭ１注入工程Ｓ７、ゲート電極Ｇ１の側壁上に側壁絶縁膜ＳＷ１を形成する工程Ｓ８、側壁絶縁膜ＳＷ１の第２加工寸法を測定する工程Ｓ９、半導体領域ＳＤ１を形成する半導体領域ＳＤ１注入工程Ｓ１０、を有する。そして、半導体領域ＳＤ１注入工程では、第１加工寸法および第２加工寸法の第１設計寸法および第２設計寸法に対する偏差に基づき、イオン注入の初期設定条件に対する実施条件を再設定して、半導体領域ＳＤ１注入工程を実施する。【選択図】図３