SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE

PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit device capable of creating a unique ID while suppressing overhead.SOLUTION: At a time of creating a unique ID, potential of a word line of a memory cell in an SRAM is set higher than power supply voltage of the SRAM and then set low...

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Bibliographic Details
Main Authors FUJIWARA HIDEHIRO, YABUUCHI MAKOTO
Format Patent
LanguageEnglish
Japanese
Published 20.07.2017
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Summary:PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit device capable of creating a unique ID while suppressing overhead.SOLUTION: At a time of creating a unique ID, potential of a word line of a memory cell in an SRAM is set higher than power supply voltage of the SRAM and then set lower than the power supply voltage of the SRAM. While the potential of the word line is set higher than the power supply voltage of the SRAM, the same data is mutually given to both bit lines of the memory cell. As a result, a state of the memory cell of the SRAM turns unstable and then changes so as to retain data according to characteristics of constituent elements and the like of the memory cell. At a time of manufacturing the SRAM, the characteristics of the constituent elements and the like of the memory cells are irregular and the respective memory cells of the SRAM retain data according to irregularity generated during the manufacturing.SELECTED DRAWING: Figure 3 【課題】オーバヘッドを抑えながら、固有IDを生成することが可能な半導体集積回路装置を提供する。【解決手段】固有IDを生成する際、SRAMのメモリセルのワード線の電位は、SRAMの電源電圧よりも高くされ、その後SRAMの電源電圧よりも低くされる。ワード線の電位が、SRAMの電源電圧よりも高くされているとき、メモリセルの両ビット線には、互いに同じデータが与えられる。これにより、SRAMのメモリセルの状態は不定状態にされた後、それを構成する素子等の特性に従ったデータを保持する様に変化する。SRAMを製造する際に、メモリセルを構成する素子等の特性は、ばらつき、SRAMのメモリセルは、その製造の際に生じるばらつきに従ったデータを保持する。【選択図】図3
Bibliography:Application Number: JP20170040110