PIPELINE TYPE ANALOG-TO-DIGITAL CONVERTER AND GAIN ERROR CORRECTION METHOD

PROBLEM TO BE SOLVED: To reduce at least one of an ADC area and power consumption.SOLUTION: In a stage 10 constituting a pipeline type analog-to-digital converter, capacitors 12, 13, 14, and 15 charge electric charges used for analog-to-digital conversion when a first voltage V1 is applied. A switch...

Full description

Saved in:
Bibliographic Details
Main Author DAITO MUTSUO
Format Patent
LanguageEnglish
Japanese
Published 13.07.2017
Subjects
BASIC ELECTRONIC CIRCUITRY
CODE CONVERSION IN GENERAL
CODING
DECODING
ELECTRICITY
Online AccessGet full text

Cover

More Information
Summary:PROBLEM TO BE SOLVED: To reduce at least one of an ADC area and power consumption.SOLUTION: In a stage 10 constituting a pipeline type analog-to-digital converter, capacitors 12, 13, 14, and 15 charge electric charges used for analog-to-digital conversion when a first voltage V1 is applied. A switch 21 is connected to the capacitor 15 and switches voltage applied to the capacitor 15 to a second voltage V2 different from the first voltage V1 in order to correct a gain error caused by the analog-to-digital conversion.SELECTED DRAWING: Figure 2 【課題】ＡＤＣの面積及び消費電力の少なくともいずれかを小さくする。【解決手段】パイプライン型アナログデジタル変換器を構成するステージ１０において、キャパシタ１２，１３，１４，１５は、第１電圧Ｖ１が印加されることで、アナログデジタル変換に用いられる電荷を充電する。スイッチ２１は、キャパシタ１５に接続され、アナログデジタル変換で生じたゲイン誤差の補正のために、キャパシタ１５に印加される電圧を第１電圧Ｖ１とは異なる第２電圧Ｖ２に切り替える。【選択図】図２
Bibliography:Application Number: JP20160001075