HOLLOW PACKAGE AND MANUFACTURING METHOD THEREOF

• Main Authors: KARASAWA YOSHIMITSU, TAKAMURA FUMIO
• Format: Patent
• Language: English; Japanese
• Published: 01.06.2017
• Subjects: BASIC ELECTRIC ELEMENTS; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; SEMICONDUCTOR DEVICES

PROBLEM TO BE SOLVED: To manufacture a package with a hollow space formed at a low cost by using a general sealing method.SOLUTION: In a dam forming step, a first dam 14 is formed on a chip 10 and a second dam 16 is formed at a position on a substrate 11 opposite to the first dam 14. In a flip chip connecting step, after connecting a bump electrodes 13 of the chip 10 to an electrodes 15 of the substrate 11 by flip chip bonding. In a resin sealing step, with a first dam 14 and a second dam 16 facing each other, a sealing resin 21 is applied between chip substrates around the chip 10, and is cured by step curing. As a result, the sealing resin 21 is well blocked by the first dam 14 and the second dam 16, so that a hollow space that does not affect the active surface of the chip 10 is formed.SELECTED DRAWING: Figure 1 【課題】一般的な封止工法を用い、かつ低コストで中空空間が形成されたパッケージを製作できるようにする。【解決手段】ダム形成工程にて、チップ１０上に第１ダム１４を形成し、かつこの第１ダム１４に対向する基板１１上の位置に第２ダム１６を形成し、フリップチップ接続工程にて、チップ１０のバンプ電極１３を基板１１の電極１５にフリップチップ接続した後、樹脂封止工程では、第１ダム１４と第２ダム１６が向かい合う状態で、チップ１０の周囲におけるチップ基板間に封止樹脂２１を塗布し、ステップキュアで硬化させる。これにより、封止樹脂２１が第１ダム１４及び第２ダム１６で良好に堰き止められるので、チップ１０のアクティブ面に影響を与えない中空空間が形成される。【選択図】図１