SEMICONDUCTOR DEVICE

PROBLEM TO BE SOLVED: To provide a semiconductor device which has increased avalanche capability while achieving low on-resistance and stable withstand voltage.SOLUTION: A semiconductor device according to an embodiment comprises first through fourth semiconductor regions. The first semiconductor re...

Full description

Saved in:
Bibliographic Details
Main Authors SUZUKI TAKUMA, NISHIO JOJI, KONO HIROSHI, SHINOHE TAKASHI
Format Patent
LanguageEnglish
Japanese
Published 20.04.2017
Subjects
Online AccessGet full text

Cover

Loading…
More Information
Summary:PROBLEM TO BE SOLVED: To provide a semiconductor device which has increased avalanche capability while achieving low on-resistance and stable withstand voltage.SOLUTION: A semiconductor device according to an embodiment comprises first through fourth semiconductor regions. The first semiconductor region has a first part and a second part and the first part is provided on a portion of the second part. The second semiconductor region is provided on an upper side of the second part and adjacent to the first part. The third semiconductor region has a high-resistance region and a low-resistance region having a resistance value lower than that of the high-resistance region, and is provided on an upper side of the portion of the second semiconductor region and away from the first part. The fourth semiconductor region is provided on an upper side of another portion of the second semiconductor region. A region out of the second semiconductor region on the side of contacting the third and fourth semiconductor regions includes a first region and a second region. The second region electrically conducting the first region and the fourth semiconductor region. The second region exists below the high-resistance region of the third semiconductor region and does not exist below the low-resistance region.SELECTED DRAWING: Figure 1 【課題】低いオン抵抗及び安定した耐圧を実現するとともに、アバランシェ耐量を高めた半導体装置を提供すること。【解決手段】実施形態に係る半導体装置は、第1〜第4半導体領域を備える。第1半導体領域は、第1部分と第2部分とを有し、第2部分の一部の上に第1部分が設けられる。第2半導体領域は、第2部分の上側であって第1部分と隣接して設けられる。第3半導体領域は、高抵抗領域と高抵抗領域よりも抵抗値の低い低抵抗領域とを有し、第2半導体領域の一部の上側であって第1部分と離間して設けられる。第4半導体領域は、第2半導体領域の別の一部の上側に設けられる。第2半導体領域のうち第3及び第4半導体領域と接する側の領域は、第1領域と第2領域とを含む。第2領域は、第1領域と第4半導体領域とを電気的に導通させる。第2領域は、第3半導体領域の高抵抗領域の下にあり、低抵抗領域の下にはない。【選択図】図1
Bibliography:Application Number: JP20160243101