PRINTED-WIRING BOARD AND METHOD FOR MANUFACTURING THE SAME

PROBLEM TO BE SOLVED: To provide a printed-wiring board with reduced void generation.SOLUTION: A printed-wiring board 10A comprises at least a conductive layer 15A including a plurality of conductor pads 25A, and an insulating layer 16A laminated on the conductive layer 15A. A via hole 28A is formed...

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Bibliographic Details
Main Author AZUMA HIROKAZU
Format Patent
LanguageEnglish
Japanese
Published 13.04.2017
Subjects
CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS
ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
PRINTED CIRCUITS
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Summary:PROBLEM TO BE SOLVED: To provide a printed-wiring board with reduced void generation.SOLUTION: A printed-wiring board 10A comprises at least a conductive layer 15A including a plurality of conductor pads 25A, and an insulating layer 16A laminated on the conductive layer 15A. A via hole 28A is formed in the insulating layer 16A so that a conductor pad 25A is exposed from the insulating layer 16A. A via conductor 18A is formed in the via hole 28A so as to come into contact with the conductor pad 25A. Surface roughness of a side wall surface 16a on which the via hole 28A is formed is smaller than surface roughness of an upper surface 16b of the insulating layer 16A.SELECTED DRAWING: Figure 1B 【課題】ボイドの生成が低減されたプリント配線板を提供する。【解決手段】プリント配線板１０Ａは、複数の導体パッド２５Ａを有した導体層１５Ａと、導体層１５Ａの上に積層された絶縁層１６Ａと、を少なくとも備える。絶縁層１６Ａには、導体パッド２５Ａが絶縁層１６Ａから露出するようにビアホール２８Ａが形成されている。ビアホール２８Ａ内には、導体パッド２５Ａと接触するようにビア導体１８Ａが形成されている。ビアホール２８Ａを形成する側壁面１６ａの表面粗さは、絶縁層１６Ａの上表面１６ｂの表面粗さよりも小さい。【選択図】図１Ｂ
Bibliography:Application Number: JP20150200687