METHOD OF MANUFACTURING SEMICONDUCTOR LAMINATE
PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor laminate, made of silicon carbide, which can reduce density of base plane dislocation in an epi layer without requiring the epi layer to be polished greatly.SOLUTION: A method of manufacturing a semiconductor laminate compris...
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Main Author | |
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Format | Patent |
Language | English Japanese |
Published |
13.04.2017
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Subjects | |
Online Access | Get full text |
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Summary: | PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor laminate, made of silicon carbide, which can reduce density of base plane dislocation in an epi layer without requiring the epi layer to be polished greatly.SOLUTION: A method of manufacturing a semiconductor laminate comprises the processes of: preparing a substrate 10 made of silicon carbide and having a first principal plane 10A which is a silicon plane having an off angle of 4° or less to a c plane; forming a pit, corresponding to dislocation included in the substrate 10, in the first principal plane 10A; and forming an epi layer 20 of silicon carbide on the first principal plane 10A having the pit formed. In the process of forming the pit, the pit of 50 nm or less in depth is formed.SELECTED DRAWING: Figure 8
【課題】エピ層の大幅な研磨を必要とすることなく、エピ層内の基底面転位の密度を低減することが可能な炭化珪素からなる半導体積層体の製造方法を提供する。【解決手段】半導体積層体の製造方法は、炭化珪素からなり、c面に対するオフ角が4°以下であるシリコン面である第1主面10Aを有する基板10を準備する工程と、第1主面10Aに、基板10に含まれる転位に対応するピットを形成する工程と、ピットが形成された第1主面10A上に、炭化珪素からなるエピ層20を形成する工程と、を備える。ピットを形成する工程では、深さ50nm以下のピットが形成される。【選択図】図8 |
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Bibliography: | Application Number: JP20150198811 |