ARITHMETIC PROCESSING DEVICE AND METHOD FOR CONTROLLING ARITHMETIC PROCESSING DEVICE

PROBLEM TO BE SOLVED: To reduce the number of times a memory is accessed to suppress the degradation of cache memory performance.SOLUTION: An arithmetic processing device comprises: a plurality of core units, each including a plurality of cores each having an arithmetic and logic unit, and a cache m...

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Main Authors ISHIMURA NAOYA, TOMATSURI HIDEAKI, KOJIMA HIROYUKI
Format Patent
LanguageEnglish
Japanese
Published 16.02.2017
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Summary:PROBLEM TO BE SOLVED: To reduce the number of times a memory is accessed to suppress the degradation of cache memory performance.SOLUTION: An arithmetic processing device comprises: a plurality of core units, each including a plurality of cores each having an arithmetic and logic unit, and a cache memory shared by the plurality of cores; a home agent operatively connected to the cache memories provided respectively in the plurality of core units; and a memory access controller connected to the home agent and controlling access to a main memory. The cache memories each includes a data memory having a plurality of cache blocks, and a first tag which stores a first state indicating a MESI state, for each of the plurality of cache blocks. The home agent includes a second tag which stores a second state including at least a shared modify state in which dirty data is shared among the plurality of cache memories, for each of the cache blocks in the cache memories provided respectively in the plurality of core units.SELECTED DRAWING: Figure 3 【課題】メモリへのアクセス回数を減らしてキャッシュメモリの性能低下を抑制する。【解決手段】それぞれ演算器を有する複数のコアと、複数のコアに共有されるキャッシュメモリとをそれぞれ備える複数のコアユニットと、複数のコアユニットがそれぞれ備えるキャッシュメモリに接続可能なホームエージェントと、ホームエージェントに接続されメインメモリとのアクセスを制御するメモリアクセスコントローラとを有し、キャッシュメモリは、複数のキャッシュブロックを有するデータメモリと、複数のキャッシュブロックそれぞれについて、MESI状態を示す第1の状態を記憶する第1のタグを備え、ホームエージェントは、複数のコアユニットがそれぞれ備えるキャッシュメモリ内の複数のキャッシュブロックそれぞれについて、少なくとも複数のキャッシュメモリがダーティなデータをシェアする共有モディファイ状態を含む第2の状態を記憶する第2のタグを備える演算処理装置。【選択図】図3
Bibliography:Application Number: JP20150159301