SEMICONDUCTOR APPARATUS MANUFACTURING METHOD, SEMICONDUCTOR APPARATUS AND SEMICONDUCTOR DEVICE

PROBLEM TO BE SOLVED: To provide a semiconductor device manufacturing method which can reduce a process which requires a special work such as a convex brim cutting process by circle cut and the like and a process which needs to handle a thin semiconductor wafer having no convex brim, and suppress ge...

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Main Authors ISHIZUKA NOBUTAKA, MIKAWA MASAHITO, UENO KENICHIRO, OSHINO HIROSHI, MATSUBARA HISAKI
Format Patent
LanguageEnglish
Japanese
Published 22.12.2016
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Summary:PROBLEM TO BE SOLVED: To provide a semiconductor device manufacturing method which can reduce a process which requires a special work such as a convex brim cutting process by circle cut and the like and a process which needs to handle a thin semiconductor wafer having no convex brim, and suppress generation of chips and cracks of a semiconductor chip and the like due to push up of the chip to inhibit deterioration in yield.SOLUTION: A semiconductor device manufacturing method includes: a semiconductor wafer preparation process S10 of preparing a semiconductor wafer 100 comprising a first principal surface 112 where an external connection electrode is formed, a convex brim 116 formed further outside an edge 114 of the first principal surface and a second principal surface 118; a conductive bonding material arrangement process S12 of arranging a conductive bonding material 120 so as to contact an external connection electrode; a grinding process S14 of grinding the semiconductor wafer from the first principal surface side until reaching the conductive bonding material 120; a tape attachment process S16 of attaching a dicing tape 122 from the first principal surface side; and a chip division process S18 of dicing the semiconductor wafer from the second principal surface side to divide the semiconductor wafer into chip units.SELECTED DRAWING: Figure 1 【課題】サークルカット等による凸状縁部切り分け工程のような特殊作業が必要な工程及び凸状縁部を欠いた薄い半導体ウエハを取り扱わなければならない工程を削減し、かつ、チップ突き上げによる半導体チップ等の割れや欠けの発生を抑制し歩留り低下を抑えることができる半導体装置の製造方法を提供する。【解決手段】外部接続電極が形成された第1主面112と第1主面の縁部114よりも更に外側に形成された凸状縁部116と第2主面118とを備えた半導体ウエハ100を準備する半導体ウエハ準備工程S10と、外部接続電極と接するように導電性接合材120を配置する導電性接合材配置工程S12と、第1主面側から導電性接合材120に達するまで研削する研削工程S14と、第1主面側からダイシングテープ122を貼り付けるテープ貼付工程S16と、第2主面側よりダイシングしてチップ単位に分割するチップ分割工程S18を含む半導体装置の製造方法。【選択図】図1
Bibliography:Application Number: JP20150100718