TIME INTERLEAVE TYPE AD CONVERTER

• Main Authors: MIKI TAKUJI, NAKA JUNICHI, OZEKI TOSHIAKI
• Format: Patent
• Language: English; Japanese
• Published: 15.12.2016
• Subjects: BASIC ELECTRONIC CIRCUITRY; CODE CONVERSION IN GENERAL; CODING; DECODING; ELECTRICITY

PROBLEM TO BE SOLVED: To provide a time interleave type AD converter that can reduce timing skew.SOLUTION: A time interleave type AD converter includes AD converters of N (N represents an integer of 2 or more) for converting an analog input voltage to a digital value, a frequency divider for dividing the frequency of a clock signal by N to generate a frequency-divided clock signal and supplying the generated frequency-divided clock signals to AD converters of N, variable delay circuits of N for adjusting the delay time of the frequency-divided clock signal supplied to each of the AD converters of N, a low pass filter circuit or input buffer circuit for limiting the band of the clock signal to generate a reference signal, and a control circuit for controlling the delay time of the variable delay circuits of N so that the errors of respective digital output values outputted from the AD converters of N when the reference signal is input are reduced to a predetermined value or less.SELECTED DRAWING: Figure 1 【課題】タイミングスキューを低減する。【解決手段】アナログ入力電圧をデジタル値に変換するＮ個（Ｎは２以上の整数）のＡＤ変換器と、クロック信号をＮ分周して分周クロック信号を生成し、生成した分周クロック信号をＮ個のＡＤ変換器に供給する分周器と、Ｎ個のＡＤ変換器にそれぞれ供給される分周クロック信号の遅延時間を調整するＮ個の可変遅延回路と、クロック信号の帯域を制限してリファレンス信号を生成する低域通過フィルタ回路または入力バッファ回路と、Ｎ個の可変遅延回路の遅延時間を制御して、リファレンス信号が入力されたときにＮ個のＡＤ変換器から出力される各デジタル出力値の誤差を所定値以下にする制御回路と、を備えたものである。【選択図】図１