SEMICONDUCTOR DEVICE

• Main Author: KAWAE DAISUKE
• Format: Patent
• Language: English; Japanese
• Published: 13.10.2016
• Subjects: BASIC ELECTRIC ELEMENTS; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; INFORMATION STORAGE; PHYSICS; SEMICONDUCTOR DEVICES; STATIC STORES

PROBLEM TO BE SOLVED: To provide a semiconductor device with the smaller area, the higher integration, and the larger storage.SOLUTION: The semiconductor device includes a first transistor, an insulating layer on the first transistor, a second transistor on the insulating layer, a first wire, a second wire, a third wire, and a conductive layer. A gate of the first transistor is electrically connected to the conductive layer. One of a source electrode and a drain electrode of the first transistor is electrically connected to the first wire. The other of the source electrode and the drain electrode of the first transistor is electrically connected to the second wire. A gate of the second transistor is electrically connected to the third wire. One of a source electrode and a drain electrode of the second transistor is electrically connected to the conductive layer. The other of the source electrode and the drain electrode of the second transistor is electrically connected to the second wire. A top surface of the insulating layer, a top surface of the conductive layer, a top surface of the source electrode of the first transistor, and a top surface of the drain electrode of the first transistor are flat.SELECTED DRAWING: Figure 4 【課題】専有面積が小さく、高集積化、大記憶容量化が可能な半導体装置を提供する。【解決手段】第１のトランジスタと、前記第１のトランジスタ上の絶縁層と、前記絶縁層上の第２のトランジスタと、第１の配線と、第２の配線と、第３の配線と、導電層と、を有し、第１のトランジスタのゲートは、前記導電層と電気的に接続され、第１のトランジスタのソース電極又はドレイン電極の一方は、前記第１の配線と電気的に接続され、第１のトランジスタのソース電極又はドレイン電極の他方は、第２の配線と電気的に接続され、第２のトランジスタのゲートは、第３の配線と電気的に接続され、第２のトランジスタのソース電極又はドレイン電極の一方は、導電層と電気的に接続され、第２のトランジスタのソース電極又はドレイン電極の他方は、第２の配線と電気的に接続され、絶縁層の上面、導電層の上面、第１のトランジスタのソース電極の上面及び第１のトランジスタのドレイン電極の上面は、平坦である半導体装置。【選択図】図４