SEMICONDUCTOR INTEGRATED CIRCUIT, PLL CIRCUIT, AND ELECTRONIC APPARATUS

• Main Authors: MITSUNAKA TAKESHI, SAITO AKIRA, ASHIDA NOBUYUKI
• Format: Patent
• Language: English; Japanese
• Published: 06.10.2016
• Subjects: AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATIONOF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES; BASIC ELECTRIC ELEMENTS; BASIC ELECTRONIC CIRCUITRY; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIRCHEMICAL OR PHYSICAL PROPERTIES; MEASURING; PHYSICS; SEMICONDUCTOR DEVICES; TESTING

PROBLEM TO BE SOLVED: To differentiate the variation of inductance of each inductor incident to the in state of a sample significantly, while reducing the circuit area.SOLUTION: In a semiconductor integrated circuit (1), a sample (S) can be placed on a protective film (91) located above the surface of a lower side substrate (93) on the side where a first inductor (110) and a second inductor (120) are formed, where the direction from the lower side substrate (93) toward the protective film (91) is the height direction. A first metal layer (ML110) forming the first inductor (110) of an oscillation circuit (11) is located at a higher position than a second metal layer (ML120) forming the second inductor (120) of a divider circuit (12).SELECTED DRAWING: Figure 1 【課題】サンプルの状態変化に伴う各インダクタのインダクタンスの変化量を有意に相異させるとともに、回路面積を低減する。【解決手段】半導体集積回路（１）において、第１インダクタ（１１０）および第２インダクタ（１２０）が形成されている側の下側基板（９３）の面の上方に配置されている保護膜（９１）上に、サンプル（Ｓ）を配置することが可能であり、下側基板（９３）から保護膜（９１）に向かう方向を高さ方向とする。発振回路（１１）の第１インダクタ（１１０）を形成する第１メタル層（ＭＬ１１０）は、分周回路（１２）の第２インダクタ（１２０）を形成する第２メタル層（ＭＬ１２０）よりも高い位置に配置されている。【選択図】図１