SEMICONDUCTOR MEMORY DEVICE

• Main Authors: MASUZAI KOJI, HASE TAKU, KOTAKE NAOYA
• Format: Patent
• Language: English; Japanese
• Published: 23.09.2016
• Subjects: BASIC ELECTRIC ELEMENTS; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; INFORMATION STORAGE; PHYSICS; SEMICONDUCTOR DEVICES; STATIC STORES

PROBLEM TO BE SOLVED: To sufficiently increase a resistance or reduce a resistance while suppressing over-writing in writing to ReRAM.SOLUTION: A semiconductor memory device comprises: a memory cell which includes a resistance change element; and a control circuit which performs Off-writing processing for applying an Off-wiring pulse Pto the memory cell in order to achieve the high resistance state and On-writing processing for applying an On-writing pulse in order to achieve the low resistance state. The control circuit applies a reading pulse for verification processing of reading out whether the memory cell is in the high resistance state or the low resistance state after applying the Off-writing pulse Pwhen the memory cell is in the low resistance state, applies the Off-writing pulse Pwith the pulse width elongated after applying a reset pulse composed of an On-writing pulse P, and then performs the verification processing when the memory cell is not in the high resistance state as a result of the verification processing.SELECTED DRAWING: Figure 7 【課題】ＲｅＲＡＭへの書込みにおいて過書込みを抑制しつつ十分に高抵抗化もしくは低抵抗化する。【解決手段】抵抗変化素子を含むメモリセルと、前記メモリセルに対して、高抵抗状態とするためにＯｆｆ書込みパルスＰｏｆｆを印加するＯｆｆ書込み処理と、低抵抗状態とするためにＯｎ書込みパルスを印加するＯｎ書込み処理とを行う制御回路とを有する。前記制御回路は、前記メモリセルが低抵抗状態の場合において、Ｏｆｆ書込みパルスＰｏｆｆを印加した後、高抵抗状態もしくは低抵抗状態のいずれであるかを読み出すベリファイ処理のための読取りパルスを印加し、前記ベリファイ処理の結果、前記メモリセルが高抵抗状態ではない場合に、Ｏｎ書込みパルスＰｏｎからなるリセットパルスを印加した後、パルス幅を長くしたＯｆｆ書込みパルスＰｏｆｆを印加して、その後前記ベリファイ処理を行う。【選択図】図７