LOGICAL PATH CONTROL SYSTEM, AND LOGICAL PATH CONTROL METHOD

• Main Authors: MISAWA AKIRA, TSUCHIYA HIDEO, MOCHIZUKI KONOMI
• Format: Patent
• Language: English; Japanese
• Published: 18.08.2016
• Subjects: ELECTRIC COMMUNICATION TECHNIQUE; ELECTRICITY; TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION

PROBLEM TO BE SOLVED: To reduce the number of logical paths.SOLUTION: A logical path control system 1 includes: a plurality of optical line terminals (OLT) 40-1, ..., 40-X; a plurality of redundant edges 50-2, ..., 50-Y, and a logical path management controller 10 for controlling logical paths between the plurality of optical line terminals 40-1, ..., 40-X and the plurality of redundant edges 50-2, ..., 50-Y. The logical path management controller 10 determines, for each of the optical line terminals 40-1, ..., 40-X, the number of logical paths to be set by the plurality of optical line terminals 40-1, ..., 40-X and sets logical paths, the number of which is the determined number, between the plurality of optical line terminals 40-1, ..., 40-X and the plurality of redundant edges 50-2, ..., 50-Y.SELECTED DRAWING: Figure 1 【課題】論理パスの数を削減することである。【解決手段】論理パス制御システム１は、複数の加入者収容装置（ＯＬＴ）４０−１、・・・、４０−Ｘと、複数の冗長エッジ５０−２、・・・、５０−Ｙと、複数の加入者収容装置４０−１、・・・、４０−Ｘと複数の冗長エッジ５０−２、・・・、５０−Ｙとの間の論理パスを制御する論理パス管理制御装置１０とを有する。論理パス管理制御装置１０は、複数の加入者収容装置４０−１、・・・、４０−Ｘが設定する上記論理パスの数を、各加入者収容装置４０−１、・・・、４０−Ｘ毎に決定すると共に、決定された数の論理パスを、複数の加入者収容装置４０−１、・・・、４０−Ｘと、複数の冗長エッジ５０−２、・・・、５０−Ｙとの間に設定する。【選択図】図１