IMAGE PROCESSOR INCLUDING PROGRAMMABLE PROCESSING SECTION, CONTROL METHOD AND PROGRAM THEREOF

PROBLEM TO BE SOLVED: To provide an image processor in which, when an FPGA is shared by two or more CPUs, a CPU other than a master which cannot control the configuration of the FPGA is capable of properly performing a piece of processing by using the FPGA during executing a piece of job processing....

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Bibliographic Details
Main Author AIDA JUNICHI
Format Patent
LanguageEnglish
Japanese
Published 08.08.2016
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Summary:PROBLEM TO BE SOLVED: To provide an image processor in which, when an FPGA is shared by two or more CPUs, a CPU other than a master which cannot control the configuration of the FPGA is capable of properly performing a piece of processing by using the FPGA during executing a piece of job processing.SOLUTION: When executing a job, a CPU other than a master switches to execute a software processing or to execute hardware processing using the FPGA based on the determination result. After executing software processing first, when receiving a notification on availability of the FPGA from a master CPU, the image processor determines whether to switch to a high speed processing using the FPGA or to the software processing depending on the remaining execution time.SELECTED DRAWING: Figure 6A 【課題】FPGAを2つ以上のCPUで共用する場合、FPGAのコンフィギュレーションを制御できないマスター以外のCPUにおいて、ジョブ処理時にFPGAを使用した処理を適切に行う。【解決手段】マスター以外のCPUは、ジョブを実行する場合に、ソフト処理を実行するか、FPGAを使用したハード処理を実行するか、判断の結果に基づき切り替えを行う。先行してソフト処理を実行し、マスターCPUからFPGA使用可能である旨の通知を受けたら、FPGAによる高速な処理に切り替えるか又はソフト処理による残りの実行時間から切り替えの判断を行う。【選択図】図６Ａ
Bibliography:Application Number: JP20150020972