SEMICONDUCTOR DEVICE MANUFACTURING METHOD

• Main Authors: SHIGIHARA HIROMI, YAJIMA KEI, AKIBA TOSHIHIKO
• Format: Patent
• Language: English; Japanese
• Published: 23.05.2016
• Subjects: BASIC ELECTRIC ELEMENTS; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; SEMICONDUCTOR DEVICES

PROBLEM TO BE SOLVED: To improve reliability of a semiconductor device and achieve downsizing of the semiconductor device.SOLUTION: A semiconductor device manufacturing method comprises the steps of: preparing a semiconductor wafer SW having a first insulating member IOL where an opening OP1 from which a top face of an electrode pad EP is exposed is formed; subsequently, forming a second insulating member OL on a principal surface of the semiconductor wafer SW; forming an opening OP2 from which the top face of the electrode pad EP is exposed in the second insulating member OL; subsequently contacting a probe needle with the electrode pad EP to write data in a memory circuit formed on the principal surface of the semiconductor wafer SW; subsequently covering the top face of the electrode pad EP with a cover film CF and subsequently forming rearrangement wiring RW. In this case, a width Lof the rearrangement wiring RW located immediately above the electrode pad EP is the same with or smaller than a width Lof the opening OP1 formed in the first insulating member IOL in a Y direction.SELECTED DRAWING: Figure 10 【課題】半導体装置の信頼性を向上し、かつ、半導体装置の小型化を実現する。【解決手段】電極パッドＥＰの上面が露出する開口部ＯＰ１が形成された第１絶縁部材ＩＯＬを有する半導体ウエハＳＷを準備する。続いて、半導体ウエハＳＷの主面上に第２絶縁部材ＯＬを形成した後、電極パッドＥＰの上面が露出する開口部ＯＰ２を第２絶縁部材ＯＬに形成した後、電極パッドＥＰにプローブ針を接触させて、半導体ウエハＳＷの主面に形成されたメモリ回路にデータを書き込む。続いて、電極パッドＥＰの上面を導電性のカバー膜ＣＦで覆った後、再配置配線ＲＷを形成する。ここで、Ｙ方向において、電極パッドＥＰの直上に位置する再配置配線ＲＷの幅ＬＲＷは、第１絶縁部材ＩＯＬに形成された開口部ＯＰ１の幅ＬＯＰ１と同じか、それよりも小さい。【選択図】図１０