METHOD AND SYSTEM FOR FORMING PIXEL ELECTRODE PATTERN

• Main Authors: YAHIRO SHUNICHI, FUJITA NAOKI, ISHIDA HIROSHI, IKEDA FUMIHIKO
• Format: Patent
• Language: English; Japanese
• Published: 19.05.2016
• Subjects: BASIC ELECTRIC ELEMENTS; DEVICES OR ARRANGEMENTS, THE OPTICAL OPERATION OF WHICH ISMODIFIED BY CHANGING THE OPTICAL PROPERTIES OF THE MEDIUM OF THEDEVICES OR ARRANGEMENTS FOR THE CONTROL OF THE INTENSITY,COLOUR, PHASE, POLARISATION OR DIRECTION OF LIGHT, e.g.SWITCHING, GATING, MODULATING OR DEMODULATING; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; FREQUENCY-CHANGING; NON-LINEAR OPTICS; OPTICAL ANALOGUE/DIGITAL CONVERTERS; OPTICAL LOGIC ELEMENTS; OPTICS; PHYSICS; SEMICONDUCTOR DEVICES; TECHNIQUES OR PROCEDURES FOR THE OPERATION THEREOF

PROBLEM TO BE SOLVED: To manufacture a liquid crystal display device of an IPS or FFS liquid crystal driving mode, and enable further reduction of the pitch between pixel electrodes with the use of a conventional general exposure device with a low resolution.SOLUTION: There is provided a method of forming a pixel electrode pattern on a glass substrate G, and including the steps of: forming, on the top face of a pixel electrode layer 1 on the glass substrate G, a resist 2 at a part to be a first space part of the pattern; forming a sacrificial film; removing the sacrificial film while leaving leftover sacrificial films 3a and 3b; and forming a second space part S2 of the pattern on the top face of the pixel electrode layer 1. The method further includes the steps of: removing the resist 2; forming the second space part of the pattern; forming resists of a contact part on the lateral side of the first space part and second space part; and removing the pixel electrode layers of the first space part and second space part.SELECTED DRAWING: Figure 3 【課題】ＩＰＳ方式、ＦＦＳ方式の液晶駆動方式等の液晶表示装置を製造するにあたり、解像度が低い従来一般の露光装置を用いても、さらなる画素電極の狭ピッチ化を可能とする。【解決手段】ガラス基板Ｇ上に画素電極のパターンを形成する方法であって、ガラス基板Ｇ上の画素電極層１の上面に、前記パターンの第１のスペース部となる部分にレジスト２を形成し、その後犠牲膜を形成し、次いで残置犠牲膜３ａ、３ｂを残して犠牲膜を除去して、画素電極層１の上面に前記パターンの第２のスペース部Ｓ２を形成する。その後レジスト２を除去して、前記パターンの第２のスペース部を形成し、次いで前記第１のスペース部、第２のスペース部の側方に、コンタクト部のレジストを形成し、その後第１のスペース部、第２のスペース部の画素電極層を除去する。【選択図】図３