SEMICONDUCTOR DEVICE MANUFACTURING METHOD

• Main Authors: OWADA FUKUO, MARUYAMA TAKAHIRO, SHINOHARA MASAAKI
• Format: Patent
• Language: English; Japanese
• Published: 28.04.2016
• Subjects: BASIC ELECTRIC ELEMENTS; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; SEMICONDUCTOR DEVICES

PROBLEM TO BE SOLVED: To provide a manufacturing method of improving performance of a semiconductor device where a nonvolatile memory as an add-on circuit is mounted in a mixed manner.SOLUTION: A semiconductor device manufacturing method comprises the steps of: forming a conductive film CF1 on an insulation film IFG which is formed in a memory formation region MR of a principal surface of a semiconductor substrate SB and has a charge storage part inside, and on an insulation film IF7 formed in a main circuit formation region AR of the principal surface of the semiconductor substrate SB; subsequently, performing patterning on the conductive film CF1 and the insulation film IFG in the memory formation region MR to form a gate electrode CG and a gate insulation film GIM and leave the conductive film CF1 and the insulation film IF7 in the main circuit formation region AR; and subsequently, performing patterning on the conductive film CF1 and the insulation film IF7 in the main circuit formation region AR to form a gate electrode GEL and a gate insulation film GIL.SELECTED DRAWING: Figure 31 【課題】アドオン回路としての不揮発性メモリを混載する半導体装置の性能を向上させる製造方法を提供する【解決手段】半導体基板ＳＢの主面のメモリ形成領域ＭＲで形成され、内部に電荷蓄積部を有する絶縁膜ＩＦＧ上、および、半導体基板ＳＢの主面の主回路形成領域ＡＲで形成された絶縁膜ＩＦ７上に、導電膜ＣＦ１を形成する。次いで、メモリ形成領域ＭＲで、導電膜ＣＦ１および絶縁膜ＩＦＧをパターニングしてゲート電極ＣＧおよびゲート絶縁膜ＧＩＭを形成し、主回路形成領域ＡＲで、導電膜ＣＦ１および絶縁膜ＩＦ７を残す。次いで、主回路形成領域ＡＲで、導電膜ＣＦ１および絶縁膜ＩＦ７をパターニングしてゲート電極ＧＥＬおよびゲート絶縁膜ＧＩＬを形成する。【選択図】図３１