SEMICONDUCTOR DEVICE

PROBLEM TO BE SOLVED: To provide a semiconductor device capable of reducing an electric field at a surface of a semiconductor region in a termination region.SOLUTION: A semiconductor device according to an embodiment comprises a first semiconductor region of a first conductivity type, a second semic...

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Bibliographic Details
Main Authors YAMASHITA HIROAKI, ONO SHOTARO, URA HIDEYUKI, IZUMISAWA MASARU
Format Patent
LanguageEnglish
Japanese
Published 25.04.2016
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Summary:PROBLEM TO BE SOLVED: To provide a semiconductor device capable of reducing an electric field at a surface of a semiconductor region in a termination region.SOLUTION: A semiconductor device according to an embodiment comprises a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type, an element region, and a termination region. The second semiconductor region is provided in the first semiconductor region. The element region includes a third semiconductor region of the second conductivity type, a fourth semiconductor region of the first conductivity type, and a gate electrode. The gate electrode is opposed to the third and fourth semiconductor regions via a gate insulating layer. The termination region has a first electrode. The termination region surrounds the element region. The first electrode has a first portion extending in a first direction, and a second portion extending in a second direction. A plurality of first electrodes are provided on the first and second semiconductor regions. An interval between the first portions adjacent in the second direction is narrower than that between the second portions adjacent in the first direction.SELECTED DRAWING: Figure 2 【課題】終端領域における半導体領域表面の電界を低減可能な半導体装置を提供する。【解決手段】実施形態の半導体装置は、第1導電形の第1半導体領域と、第2導電形の第2半導体領域と、素子領域と、終端領域と、を有する。第2半導体領域は、第1半導体領域内に設けられている。素子領域は、第2導電形の第3半導体領域と、第1導電形の第4半導体領域と、ゲート電極と、を有する。ゲート電極は、ゲート絶縁層を介して、第3半導体領域及び第4半導体領域に向かい合っている。終端領域は、第1電極を有する。終端領域は、素子領域を囲んでいる。第1電極は、第1方向に延びる第1部分と、第2方向に延びる第2部分と、を有する。第1電極は、第1半導体領域上及び第2半導体領域上に複数設けられている。第2方向において隣り合う第1部分の間隔は、第1方向において隣り合う第2部分の間隔よりも狭い。【選択図】図2
Bibliography:Application Number: JP20140187330