SEMICONDUCTOR DEVICE

• Main Author: KAMATA SHUJI
• Format: Patent
• Language: English; Japanese
• Published: 22.03.2016
• Subjects: BASIC ELECTRIC ELEMENTS; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; SEMICONDUCTOR DEVICES

PROBLEM TO BE SOLVED: To provide a semiconductor device with suppressed reduction in switching speed.SOLUTION: The semiconductor device according to an embodiment comprises: a semiconductor substrate that has a first surface and a second surface; a first semiconductor layer of a first conductivity type provided on the first surface side; a second semiconductor layer of a second conductivity type provided at the second surface side of the first semiconductor layer; a third semiconductor layer of the first conductivity type provided at the second surface side of the second semiconductor layer; a plurality of gate layers provided in the semiconductor substrate; a plurality of first semiconductor regions of the second conductivity type provided in the third semiconductor layer between adjacent first and second gate layers among the plurality of gate layers; a second semiconductor region of the first conductivity type provided between the first semiconductor regions; a gate insulating film that is provided between the first gate layer, and the second semiconductor layer, the third semiconductor layer, the first semiconductor region, and the second semiconductor region, and that is formed in such a way that the a film thickness between the gate insulating film and the second semiconductor region is thicker than a film thickness between the gate insulating film and the first semiconductor region; an emitter electrode; and a collector electrode.SELECTED DRAWING: Figure 1 【課題】スイッチングスピードの低下を抑制する半導体装置を提供する。【解決手段】実施形態の半導体装置は、第１の面と第２の面を有する半導体基板と、第１の面側に設けられる第１導電型の第１の半導体層と、第１の半導体層の第２の面側に設けられる第２導電型の第２の半導体層と、第２の半導体層の第２の面側に設けられる第１導電型の第３の半導体層と、半導体基板内部に設けられる複数のゲート層と、複数のゲート層のうちの隣接する第１のゲート層と第２のゲート層との間の第３の半導体層に設けられる複数の第２導電型の第１の半導体領域と、第１の半導体領域の間に設けられる第１導電型の第２の半導体領域と、第１のゲート層と、第２の半導体層、第３の半導体層、第１の半導体領域及び第２の半導体領域との間に設けられ、第２の半導体領域との間の膜厚が第１の半導体領域との間の膜厚よりも厚いゲート絶縁膜と、エミッタ電極と、コレクタ電極と、を備える。【選択図】図１