SEMICONDUCTOR DEVICE

PROBLEM TO BE SOLVED: To provide a technology which improves the visibility of an alignment mark thereby enabling high accuracy positioning between a semiconductor chip and a mounting substrate.SOLUTION: In a semiconductor chip forming an LCD driver, a mark MK1 is formed at an alignment mark formati...

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Bibliographic Details
Main Authors KOKETSU MASAMI, SAWADA TOSHIAKI
Format Patent
LanguageEnglish
Japanese
Published 17.12.2015
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Summary:PROBLEM TO BE SOLVED: To provide a technology which improves the visibility of an alignment mark thereby enabling high accuracy positioning between a semiconductor chip and a mounting substrate.SOLUTION: In a semiconductor chip forming an LCD driver, a mark MK1 is formed at an alignment mark formation region on a semiconductor substrate 1S. The mark MK1 is formed by the same layer as top layer wiring (a third layer wiring L3) of an integrated circuit formation region. Patterns P1a, P1b, P2, P3 are formed at lower layers of the mark MK1 and a background region enclosing the mark MK1. The pattern P1a is formed by the same layer as second layer wiring L2. The pattern P1b is formed as the same layer as first wiring L1. Further, the pattern P2 is formed by the same layer as a gate electrode G and the pattern P3 is formed by the same layer as an element separation region STI. 【課題】アライメントマークの視認性を向上することにより、半導体チップと実装基板との位置合わせを高精度に行なうことができる技術を提供する。【解決手段】ＬＣＤドライバを構成する半導体チップにおいて、半導体基板１Ｓ上のアライメントマーク形成領域にマークＭＫ１を形成する。このマークＭＫ１は、集積回路形成領域の最上層配線（第３層配線Ｌ３）と同層で形成されている。そして、マークＭＫ１およびマークＭＫ１を囲む背景領域の下層にパターンＰ１ａ、Ｐ１ｂ、Ｐ２、Ｐ３を形成する。このとき、パターンＰ１ａは第２層配線Ｌ２と同層で形成されており、パターンＰ１ｂは、第１層配線Ｌ１と同層で形成されている。さらに、パターンＰ２は、ゲート電極Ｇと同層で形成されており、パターンＰ３は素子分離領域ＳＴＩと同層で形成される。【選択図】図９
Bibliography:Application Number: JP20150172420