SEMICONDUCTOR DEVICE

PROBLEM TO BE SOLVED: To provide a semiconductor device having improved withstand voltage.SOLUTION: A semiconductor device 100 includes a substrate 10, a first conductive layer 20, a diffusion layer 30, a first insulation layer 40, a second conductive layer 50, a second insulation layer 60 and a thi...

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Bibliographic Details
Main Author SEKIGUCHI HIDEKI
Format Patent
LanguageEnglish
Japanese
Published 05.10.2015
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Summary:PROBLEM TO BE SOLVED: To provide a semiconductor device having improved withstand voltage.SOLUTION: A semiconductor device 100 includes a substrate 10, a first conductive layer 20, a diffusion layer 30, a first insulation layer 40, a second conductive layer 50, a second insulation layer 60 and a third insulation layer 70. The substrate has a principal surface 10p and includes an inside region 11 including a semiconductor element and an outside region 12 around the inside region. The first conductive layer is provided above the outside region and includes a first outside conductive part 21 and a first inside conductive part 22. The diffusion layer is provided in the outside region and includes an outside diffusion part 31 and an inside diffusion part 32 which lie between the inside region and the first outside conductive part when projected on the principal surface. The first insulation layer is provided between the first outside conductive part and the outside region and includes an outside insulation part 41 and an inside insulation part 42 which lies between the outside insulation part and the outside diffusion part when projected on the principal surface. The second conductive layer is provided between the outside region and the first outside conductive part and includes a second outside conductive part 51 between the inside insulation part and the first outside conductive part, a second inside conductive part 52 between the outside diffusion part and the first inside conductive part, and an intermediate conductive part 53. 【課題】耐圧を向上させた半導体装置を提供する。【解決手段】半導体装置100は、基板10と第1導電層20と拡散層30と第1絶縁層40と第2導電層50と第2絶縁層60と第3絶縁層70とを含む。基板は主面10pを有し、半導体素子を含む内側領域11とその周りの外側領域12とを含む。第1導電層は外側領域の上に設けられ、第1外側導電部21と第1内側導電部22とを含む。拡散層は外側領域に設けられ、主面に投影した時に内側領域と第1外側導電部との間の外側拡散部31と、内側拡散部32を含む。第1絶縁層は第1外側導電部と外側領域の間に設けられ、外側絶縁部41と主面に投影した時に外側絶縁部と外側拡散部の間の内側絶縁部42を含む。第2導電層は外側領域と第1外側導電部の間に設けられ、内側絶縁部と第1外側導電部の間の第2外側導電部51と、外側拡散部と第1内側導電部の間の第2内側導電部52と中間導電部53を含む。【選択図】図2
Bibliography:Application Number: JP20140052565