NONVOLATILE SEMICONDUCTOR STORAGE DEVICE
PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor storage device that can reduce writing disturbance.SOLUTION: A nonvolatile semiconductor storage device comprises: first and second columnar semiconductors that are arranged on a semiconductor layer and extend in a normal direction relativ...
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Main Author | |
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Format | Patent |
Language | English Japanese |
Published |
05.10.2015
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Subjects | |
Online Access | Get full text |
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Summary: | PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor storage device that can reduce writing disturbance.SOLUTION: A nonvolatile semiconductor storage device comprises: first and second columnar semiconductors that are arranged on a semiconductor layer and extend in a normal direction relative to the semiconductor layer; a memory cell (MC) that includes the first and second columnar semiconductors (SC) via a gate insulator film, and includes an electric charge accumulation layer and a control gate; first and second selection transistors that are formed so as to sandwich the memory cell; a memory cell array that plurally includes a memory string (MS) including a back gate transistor (BG) parallely connected to the first and second selection transistors; and a control unit that applies a writing voltage to the memory cell prior to a writing operation for applying the writing voltage to the first selection transistor (ST1).
【課題】書き込みディスターブを低減可能とする不揮発性半導体記憶装置を提供する。【解決手段】半導体層上に配置され、前記半導体層に対する法線方向に延びた第1柱状半導体及び第2柱状半導体、ゲート絶縁膜を介して前記第1及び第2柱状半導体(SC)を含み、電荷蓄積層及び制御ゲートを含むメモリセル(MC)、前記メモリセルを挟むように形成された第1、及び第2選択トランジスタ、前記第1選択トランジスタと前記第2選択トランジスタに直列に接続されたバックゲートトランジスタ(BG)を含むメモリストリング(MS)を複数含むメモリセルアレイと、前記第1選択トランジスタ(ST1)に書き込み電圧を印加する書き込み動作の前に、前記メモリセルに書き込み電圧を印加する制御部とを具備する。【選択図】図6 |
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Bibliography: | Application Number: JP20140052687 |