SEMICONDUCTOR DEVICE
PROBLEM TO BE SOLVED: To provide a semiconductor device capable of reducing an on-resistance.SOLUTION: A semiconductor device comprises: a first semiconductor layer of a first conductivity type provided between a drain electrode and a source electrode; a second semiconductor layer provided between t...
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Main Authors | , , , |
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Format | Patent |
Language | English Japanese |
Published |
23.07.2015
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Subjects | |
Online Access | Get full text |
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Summary: | PROBLEM TO BE SOLVED: To provide a semiconductor device capable of reducing an on-resistance.SOLUTION: A semiconductor device comprises: a first semiconductor layer of a first conductivity type provided between a drain electrode and a source electrode; a second semiconductor layer provided between the first semiconductor layer and the source electrode, and having a concentration of impurity of the first conductivity type higher than that of the first semiconductor layer; a plurality of third semiconductor layers of a second conductivity type whose drain electrode side end parts are provided on the first semiconductor layer, and that are provided so as to be contacted with the first semiconductor layer and the second semiconductor layer; a fourth semiconductor layer of the second conductivity type provided between the second semiconductor layer and the source electrode; a fifth semiconductor layer of the first conductivity type provided between the fourth semiconductor layer and the source electrode; a field plate electrode provided so as to interpose a first insulating film between itself and the second semiconductor layer; and a gate electrode provided so as to interpose a second insulating film having a film thickness thinner than that of the first insulating film, between itself and the fourth semiconductor layer.
【課題】オン抵抗の低減を可能とする半導体装置を提供する。【解決手段】実施形態の半導体装置は、ドレイン電極とソース電極との間に設けられる第1導電型の第1の半導体層と、第1の半導体層とソース電極との間に設けられ、第1の半導体層よりも第1導電型の不純物濃度が高い第2の半導体層と、ドレイン電極側の端部が第1の半導体層にあり、第1の半導体層および第2の半導体層に接して設けられる複数の第2導電型の第3の半導体層と、第2の半導体層とソース電極との間に設けられる第2導電型の第4の半導体層と、第4の半導体層とソース電極との間に設けられる第1導電型の第5の半導体層と、第2の半導体層との間に、第1の絶縁膜を介して設けられるフィールドプレート電極と、第4の半導体層との間に、第1の絶縁膜よりも膜厚が薄い第2の絶縁膜を介して設けられるゲート電極と、を備える。【選択図】図1 |
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Bibliography: | Application Number: JP20140003369 |