SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE

• Main Authors: NAKAMICHI MASARU, KITAI NAOKI, NISHIDA AKIO, OSADA KENICHI, ISHIBASHI KOICHIRO, SAITO YOSHIKAZU
• Format: Patent
• Language: English; Japanese
• Published: 23.07.2015
• Subjects: ELECTRICITY; INFORMATION STORAGE; PHYSICS; STATIC STORES

PROBLEM TO BE SOLVED: To solve a problem due to an increase in gate tunnel leakage current of an MOS in a leading-edge process for the semiconductor device requiring a standby mode at low leakage current.SOLUTION: A semiconductor integrated circuit device includes a power supply voltage control circuit for controlling the power supply voltage of a plurality of static type memory cells which is a potential difference between a power supply line and a source line. The power supply voltage control circuit controls the potential of the source line so that when first and second N channel transfer MOS transistors constituting the memory cells are in an off state, a GIDL current flowing through the first and second N channel transfer MOS transistors is smaller in a standby state than in an operating state. 【課題】先端プロセスではＭＯＳのゲートトンネルリーク電流が増大し、低リーク電流での待機が必要となる半導体装置では問題となる。【解決手段】電源線とソース線との電位差である複数のスタティック型メモリセルの電源電圧を制御する電源電圧制御回路を具備する。電源電圧制御回路は前記ソース線の電位を制御することにより、前記メセルセルを構成する第１及び第２のトランスファーＮチャネルＭＯＳトランジスタがオフ状態の際に、第１及び第２のトランスファーＮチャネルＭＯＳトランジスタに流れるＧＩＤＬ電流が動作状態に対して待機状態の方が小さくする。【選択図】図５