SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE

• Main Authors: ARAI KOJI, YAMAOKA MASANAO, SHIMAZAKI YASUHISA, MAEDA NORIAKI, SHINOZAKI YOSHIHIRO, ISODA MASANORI
• Format: Patent
• Language: English; Japanese
• Published: 18.06.2015
• Subjects: BASIC ELECTRIC ELEMENTS; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; INFORMATION STORAGE; PHYSICS; SEMICONDUCTOR DEVICES; STATIC STORES

PROBLEM TO BE SOLVED: To provide an SRAM capable of realizing both SNM and write margin even at low power supply voltage.SOLUTION: An SRAM includes: memory cell power supply lines; a power supply line for supplying a power supply voltage; and a power supply circuit provided to correspond to the cell power supply lines and electrically connecting the memory cell power supply lines to the power supply line. Each memory cell is constituted by a CMOS latch circuit that includes first and second P-channel transistors, first to fourth N-channel transistors, and first and second storage nodes. The memory cell area is a rectangular area, and contact holes connected to sources of the first and second P-channel transistors and contact holes connected to gates of the third and fourth N-channel transistors are arranged on respective sides of the rectangular area. The power supply circuit reduces a voltage of the memory cell power supply lines at a time of writing data to any of the memory cells. 【課題】低電源電圧でもＳＮＭと書き込みマージンを両立させたＳＲＡＭを備える。【解決手段】ＳＲＡＭは、セル電源線、電源電圧を供給する電源線、及びセル電源線に対応して設けられ、メモリセル電源線と前記電源線との間を電気的に接続する電源回路を含む。メモリセルの各々は、第１及び第２のＰチャネル型トランジスタと、第１ないし第４のＮチャネル型トランジスタと第１及び第２の記憶ノードとを有するＣＭＯＳラッチ回路で構成される。前記メモリセル領域は矩形領域であり、第１及び第２のＰャネル型トランジスタのそれぞれのソースに接続されるコンタクトホール、並びに第３及び第４のＮチャネル型トランジスタのそれぞれのゲートに接続されるコンタクトホールはそれぞれ矩形領域の各辺に配置される。前記電源回路は、前記複数のメモリセルのいずれかにデータを書き込む際には前記メモリセル電源線の電圧を下げる。【選択図】図４