SEMICONDUCTOR DEVICE MANUFACTURING METHOD AND SEMICONDUCTOR DEVICE

• Main Authors: NAKAMURA HIROKI, MASUOKA FUJIO
• Format: Patent
• Language: English; Japanese
• Published: 09.04.2015
• Subjects: BASIC ELECTRIC ELEMENTS; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; SEMICONDUCTOR DEVICES

PROBLEM TO BE SOLVED: To provide a manufacturing method of an SGT which forms a fin-shaped semiconductor layer, a columnar semiconductor layer, a gate electrode and gate wiring by using two masks, and which is a gate last process; and provide a structure of the SGT obtained as a result.SOLUTION: A semiconductor device manufacturing method comprises: a first process of forming a fin-shaped semiconductor layer on a semiconductor substrate and forming a first insulation film around the fin-shaped semiconductor layer; and a second process of forming a second insulation film around the fin-shaped semiconductor layer after the first process, depositing and planarizing a first polysilicon on the second insulation film, forming a second resist for forming gate wiring and a columnar semiconductor layer in a direction perpendicular to a direction of the fin-shaped semiconductor layer, and etching the first polysilicon, the second insulation film and the fin-shaped semiconductor layer to form the columnar semiconductor layer and a first dummy gate by the first polysilicon. 【課題】２個のマスクで、フィン状半導体層、柱状半導体層、ゲート電極とゲート配線を形成し、ゲートラストプロセスであるＳＧＴの製造方法とその結果得られるＳＧＴの構造を提供する。【解決手段】半導体基板上にフィン状半導体層を形成し、前記フィン状半導体層の周囲に第１の絶縁膜を形成する第１工程と、前記第１工程の後、前記フィン状半導体層の周囲に第２の絶縁膜を形成し、前記第２の絶縁膜の上に第１のポリシリコンを堆積し平坦化し、ゲート配線と柱状半導体層を形成するための第２のレジストを、前記フィン状半導体層の方向に対して垂直の方向に形成し、前記第１のポリシリコンと前記第２の絶縁膜と前記フィン状半導体層をエッチングすることにより、柱状半導体層と前記第１のポリシリコンによる第１のダミーゲートを形成する第２工程とにより、上記課題を解決する。【選択図】図１