SEMICONDUCTOR STORAGE DEVICE

• Main Authors: IWATA YOSHIHISA, TANAKA CHIKA, ICHIHARA REIKA
• Format: Patent
• Language: English; Japanese
• Published: 30.03.2015
• Subjects: INFORMATION STORAGE; PHYSICS; STATIC STORES

PROBLEM TO BE SOLVED: To provide a semiconductor storage device capable of suppressing deterioration of memory cells.SOLUTION: A semiconductor storage device of an embodiment includes: a plurality of first wirings; a plurality of second wirings extending so as to intersect the first wirings; a plurality of memory cells which are arranged at each of intersections of the first wirings and second wirings and include a variable resistive element; and a control circuit that controls voltage to be applied to the memory cells. The control circuit is configured to execute a set operation in which a set voltage is applied to a selected memory cell that is connected to a selected first wiring and selected second wiring when the set operation for changing the memory cells to a set state is performed. The control circuit is configured to execute an additional set operation in which a voltage application time of the set voltage is changed according to the state of change in the selected memory cell during the set operation and the set voltage is applied to the selected memory cell. 【課題】メモリセルの劣化を抑制することのできる半導体記憶装置を提供する。【解決手段】一の実施の形態に係る半導体記憶装置は、複数の第１配線と、前記第１配線に交差するように延びる複数の第２配線と、前記第１配線と前記第２配線との各交差部に配置され可変抵抗素子を含む複数のメモリセルと、前記メモリセルに印加する電圧を制御する制御回路とを備える。前記制御回路は、前記メモリセルをセット状態に変化させるセット動作時に、選択第１配線及び選択第２配線に接続された選択メモリセルにセット電圧を印加するセット動作を実行可能に構成されている。前記制御回路は、前記セット動作時の前記選択メモリセルの変化の状態に応じて前記セット電圧の電圧印加時間を変更して、前記選択メモリセルに前記セット電圧を印加する追加セット動作を実行可能に構成されている。【選択図】図７