SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME

• Main Authors: SAKUMA YU, FUKUZUMI YOSHIAKI
• Format: Patent
• Language: English; Japanese
• Published: 12.02.2015
• Subjects: BASIC ELECTRIC ELEMENTS; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; SEMICONDUCTOR DEVICES

PROBLEM TO BE SOLVED: To provide a semiconductor memory device that allows improving the reliability of a memory cell, and a method of manufacturing the same.SOLUTION: A stacked body has a plurality of electrode layers and a plurality of insulating layers that are alternately stacked on a substrate. The stacked body further has hierarchy selection portions each having a plurality of row portions and a plurality of contact portions connected to each layer of the electrode layers at ends of the row portions in a first direction. Selection transistors are provided between a memory array region in which a channel body and a memory film are provided and the hierarchy selection portions, and select the row portions. The selection transistors are provided on side walls of the row portions between the memory array region and the hierarchy selection portions and each have a gate electrode extending in the stacking direction. 【課題】実施形態は、メモリセルの信頼性を向上させることができる半導体記憶装置及びその製造方法を提供する。【解決手段】実施形態によれば、積層体は、基板上にそれぞれ交互に積層された複数の電極層と複数の絶縁層とを有する。積層体は、複数の列部と、列部の第１の方向の端で各層の電極層に接続された複数のコンタクト部を有する階層選択部とを有する。選択トランジスタは、チャネルボディ及びメモリ膜が設けられたメモリアレイ領域と、階層選択部との間に設けられ、列部を選択する。選択トランジスタは、メモリアレイ領域と階層選択部との間の列部の側壁に設けられ、積層方向に延びるゲート電極を有する。【選択図】図１