SEMICONDUCTOR MEMORY DEVICE

PROBLEM TO BE SOLVED: To provide a semiconductor memory device having compatibility with DRAM.SOLUTION: A semiconductor memory device receives a row address RA and a column address CA at the same time in synchronization with an active command; and receives a page address PA in synchronization with a...

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Bibliographic Details
Main Authors MAE KENJI, KATAGIRI MASASHI
Format Patent
LanguageEnglish
Published 26.06.2014
Subjects
INFORMATION STORAGE
PHYSICS
STATIC STORES
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Summary:PROBLEM TO BE SOLVED: To provide a semiconductor memory device having compatibility with DRAM.SOLUTION: A semiconductor memory device receives a row address RA and a column address CA at the same time in synchronization with an active command; and receives a page address PA in synchronization with a read command or write command. Word drivers 31to 31select a word line WL on the basis of the row address RA; and column switches 32-32select bit lines BL on the basis of the column address CA. A page address decoder 43 selects any one of read/write amplifiers 33-33corresponding to each of pages P0 to P511, on the basis of the page address PA. Thus, DRAM specs such as an access cycle can be satisfied without providing an amplifier for each bit line, thereby enabling compatibility with a DRAM to be ensured while reducing a chip area.
Bibliography:Application Number: JP20140019918