INPUT CIRCUIT

PROBLEM TO BE SOLVED: To provide an input circuit that can suppress an increase in a signal propagation delay time.SOLUTION: An input circuit 10 includes a P channel MOS transistor TP1 having a first terminal connected to a power line L1 and a second terminal connected to a node N2, and a P channel...

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Bibliographic Details
Main Author UNO OSAMU
Format Patent
LanguageEnglish
Published 29.05.2014
Subjects
BASIC ELECTRONIC CIRCUITRY
ELECTRICITY
PULSE TECHNIQUE
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Summary:PROBLEM TO BE SOLVED: To provide an input circuit that can suppress an increase in a signal propagation delay time.SOLUTION: An input circuit 10 includes a P channel MOS transistor TP1 having a first terminal connected to a power line L1 and a second terminal connected to a node N2, and a P channel MOS transistor TP2 having a first terminal connected to the node N2 and a second terminal connected to a node N1. The input circuit 10 includes an N channel MOS transistor TN1 having a first terminal connected to the node N1 and a second terminal connected to a node N3, and an N channel MOS transistor TN2 having a first terminal connected to the node N3 and a second terminal connected to a power line L2. The transistors TP1, TP2, TN1, TN2 have gate terminals fed with an input signal Vin. The input circuit 10 includes a control circuit 15 for controlling potentials of the nodes N2, N3 on the basis of the input signal Vin and a voltage V1 of the node N1.
Bibliography:Application Number: JP20120249182