METHOD OF MAKING LOGIC TRANSISTOR AND NON-VOLATILE MEMORY (NVM) CELL

• Main Authors: HALL MARK D, FRANK K BAKER JR, MEHUL D SHROFF
• Format: Patent
• Language: English
• Published: 12.05.2014
• Subjects: BASIC ELECTRIC ELEMENTS; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; SEMICONDUCTOR DEVICES

PROBLEM TO BE SOLVED: To provide a method of making a logic transistor and a non-volatile memory (NVM) cell.SOLUTION: An oxide-containing layer is formed directly on a semiconductor layer in an NVM region (14), and a first partial layer of a first material is formed over the oxide-containing layer in the NVM region. A first high-K dielectric layer is formed directly on the semiconductor layer in a logic region (16). A first conductive layer is formed over the first dielectric layer in the logic region. A second partial layer of the first material is formed directly on the first partial layer in the NVM region and over the first conductive layer in the logic region. A logic device is formed in the logic region. An NVM cell is formed in the NVM region, and the first and second partial layers together are used to form one of a charge storage layer if the cell is a floating gate cell or a select gate if the cell is a split gate cell.