SEMICONDUCTOR DEVICE

PROBLEM TO BE SOLVED: To suppress increase in SRAM cell area, while getting the enhancement effect of soft error tolerance.SOLUTION: A capacitor CG1 is connected with the storage node NA of an SRAM cell 160. The capacitor CG1 is a P channel type MIS capacitor. The capacitor CG1 has a MIS(Metal Insul...

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Bibliographic Details
Main Author OBATA HIROYUKI
Format Patent
LanguageEnglish
Published 20.01.2014
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
INFORMATION STORAGE
PHYSICS
SEMICONDUCTOR DEVICES
STATIC STORES
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Summary:PROBLEM TO BE SOLVED: To suppress increase in SRAM cell area, while getting the enhancement effect of soft error tolerance.SOLUTION: A capacitor CG1 is connected with the storage node NA of an SRAM cell 160. The capacitor CG1 is a P channel type MIS capacitor. The capacitor CG1 has a MIS(Metal Insulator Semiconductor) structure which has an N type semiconductor region (61), an insulation layer (51) formed on the surface region (611) of the N type semiconductor region (61), a gate conductive layer (311) formed on the insulation layer (51), and a P type diffusion region (231) formed contiguously to the surface region (611), but in which a P type diffusion region is not formed at a position symmetrical to the P type diffusion region (231) with respect to the surface region (611).
Bibliography:Application Number: JP20120149504