PARTITION-FREE MULTI-SOCKET MEMORY SYSTEM ARCHITECTURE

PROBLEM TO BE SOLVED: To provide a technique to increase the memory bandwidth for applications.SOLUTION: An apparatus comprises at least two processors coupled to at least two memories. A first processor 200 of the at least two processors is configured to read a first portion of data stored in a fir...

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Bibliographic Details
Main Author SPRANGLE ERIC
Format Patent
LanguageEnglish
Published 09.09.2013
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Summary:PROBLEM TO BE SOLVED: To provide a technique to increase the memory bandwidth for applications.SOLUTION: An apparatus comprises at least two processors coupled to at least two memories. A first processor 200 of the at least two processors is configured to read a first portion of data stored in a first memory 225 of the at least two memories and a second portion of data stored in a second memory 220 of the at least two memories within a first portion of a clock signal period. A second processor 205 of the at least two processors is configured to read a third portion of data stored in the first memory 225 of the at least two memories and a fourth portion of data stored in the second memory 220 of the at least two memories within the first portion of the clock signal period.
Bibliography:Application Number: JP20130111885