PIPELINE ANALOG TO DIGITAL CONVERTER WITH REDUCED POWER CONSUMPTION

• Main Author: DOUGLAS A GARRITY
• Format: Patent
• Language: English
• Published: 01.08.2013
• Subjects: BASIC ELECTRONIC CIRCUITRY; CODE CONVERSION IN GENERAL; CODING; DECODING; ELECTRICITY

PROBLEM TO BE SOLVED: To provide a pipeline analog to digital (A/D) converter which has both advantages of a high input sample rate and low power consumption by allowing all pipeline stages, excepting for a first pipeline stage, to operate in a frequency that is a certain fraction of an input sample rate.SOLUTION: A first stage 110 has an internal operation frequency that is a sample rate for all A/D converters and samples an input signal on the same clock edge in each sample. A subsequent pipeline stage 120 includes a parallel input sampling circuit which samples a provided input signal at a reduced rate. The input sampling circuit operates in a reduced frequency, thereby reducing power consumed by these stages. The input signal is sampled on the same clock edge for each sample, thereby solving the problem of frequency response image generated relating to an A/D converter architecture sampling an input signal on two or more clock edges.