SEMICONDUCTOR DEVICE

PROBLEM TO BE SOLVED: To provide a semiconductor device capable of detecting clock cycle variation of a signal output from a memory circuit to a self-test circuit or a signal within the self-test circuit.SOLUTION: A self-test circuit includes: test pattern generating means for generating a pseudo ex...

Full description

Saved in:
Bibliographic Details
Main Author MAENO HIDESHI
Format Patent
LanguageEnglish
Published 04.07.2013
Subjects
INFORMATION STORAGE
PHYSICS
STATIC STORES
Online AccessGet full text

Cover

More Information
Summary:PROBLEM TO BE SOLVED: To provide a semiconductor device capable of detecting clock cycle variation of a signal output from a memory circuit to a self-test circuit or a signal within the self-test circuit.SOLUTION: A self-test circuit includes: test pattern generating means for generating a pseudo expected value signal, which comprises a bit value, in each clock cycle, in a bit stream obtained by inverting some of bit values in a bit stream of an expected value of a bit value of an output data signal from a memory circuit in each clock cycle, and for generating a compare enable signal; and comparison means for receiving the output data signal from the memory circuit, and the pseudo expected value signal and the compare enable signal from the test pattern generating means to compare the output data signal and the pseudo expected value signal in each clock cycle while the compare enable signal is active. The self-test circuit stores a bit value of a comparison result signal, which represents a result of the comparison in each clock cycle.
Bibliography:Application Number: JP20110280975