SIGNAL EQUALIZER

PROBLEM TO BE SOLVED: To provide a signal equalizer that has an inexpensive and simple configuration.SOLUTION: The signal equalizer includes: strip wiring 3 connected at one end to a transmission end 1 to transmit a signal; an equalizer circuit 6 comprising an FET 12 having a source terminal S conne...

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Bibliographic Details
Main Authors AKEBOSHI YOSHIHIRO, OHASHI HIDEMASA, SUZUKI KATSUMSA
Format Patent
LanguageEnglish
Published 17.06.2013
Subjects
BASIC ELECTRONIC CIRCUITRY
ELECTRICITY
IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS
RESONATORS
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Summary:PROBLEM TO BE SOLVED: To provide a signal equalizer that has an inexpensive and simple configuration.SOLUTION: The signal equalizer includes: strip wiring 3 connected at one end to a transmission end 1 to transmit a signal; an equalizer circuit 6 comprising an FET 12 having a source terminal S connected to the other end of the strip wiring 3 and a drain terminal D connected to a reception end 2, and a resistance 13 connected between the drain and source terminals of the FET 12; and a gate voltage control circuit 15 for controlling a gate voltage of the FET 12 to control on/off the FET 12. The signal equalizer is configured to remove a low frequency component of the transmission signal transmitted through the strip wiring 3 when the gate voltage control circuit 15 controls the FET 12 of the equalizer circuit 6 to an off state. The equalizer circuit 6 can comprise one FET 12 and one resistance 13 to implement an inexpensive and simple configuration.
Bibliography:Application Number: JP20110269088