METHOD FOR INSPECTING SEMICONDUCTOR INTEGRATED CIRCUIT, AND THE SEMICONDUCTOR INTEGRATED CIRCUIT

• Main Author: SHOYAMA HIDEKI
• Format: Patent
• Language: English
• Published: 13.05.2013
• Subjects: BASIC ELECTRIC ELEMENTS; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; MEASURING; MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES; PHYSICS; SEMICONDUCTOR DEVICES; TESTING

PROBLEM TO BE SOLVED: To inspect random logic of a semiconductor integrated circuit by dynamically changing an inner clock of the semiconductor integrated circuit while supplying only a clock of a fixed frequency to the clock of the semiconductor integrated circuit.SOLUTION: An inspection method of a semiconductor integrated circuit including a plurality of combination circuits and a plurality of scan flip-flops composing a scan chain for performing scan tests of the plurality of combination circuits includes: an input step for inputting a first clock of a fixed frequency from a clock generation device to the semiconductor integrated circuit; a frequency division step for generating a second clock by dividing the frequency of the first clock by a frequency divider included in the semiconductor integrated circuit; and an inspection step for inspecting the semiconductor integrated circuit while dynamically switching a clock to be inputted to the plurality of scan flip-flops between the first clock and the second clock.